MT88E46ASR1 Datasheet MT88E46ASR1, MT88E46AS1 | P1-P3

Zarlink Semiconductor Inc.

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MT88E46

Bellcore Compliant Calling Number

Identification Circuit

Data Sheet

Features

• Compatible with Bellcore GR-30-CORE, SR-

TSV-002476; TIA/EIA-716 and TIA/EIA-777

• Pin compatible with MT88E45

• Differential input amplifiers with adjustable gains

for Tip/Ring and 4-wire side connections

• TIA (Telecommunications Industry Association)

MEI (Multiple Extension Interworking) compatible

architecture: CAS (CPE Alerting Signal) detection

is selectable between Tip/Ring and 4-wire side

• 4-wire side CAS detection is Bellcore talkoff and

talkdown compliant when near end speech is

attenuated 8 dB or better, and is close to talkoff

compliant even without near end speech attenuation

• Tip/Ring side CAS detection typically meets

talkdown condition 1 (the average case)

• 1200 baud Bell 202 and CCITT V.23 FSK

demodulation

• Selectable 3-wire FSK data interface (serial bit

stream or 1 byte buffer) with facility to monitor stop

bit for framing error check

• FSK carrier detect status output

•3 to 5V ± 10% supply voltage

• Uses 3.579545 MHz crystal

• Low power CMOS with power down mode

Applications

• Bellcore compliant CIDCW (Calling Identity

Delivery on Call Waiting) and CWD (Call Waiting

Deluxe) telephones

• CIDCW and CWD telephone adjunct boxes

• Computer Telephony Integrated (CTI) systems

Description

The MT88E46 is a CMOS integrated circuit suitable for

receiving the FSK and CAS signals in North American

(Bellcore) CIDCW, CWD and CID (Calling Identity

Delivery) services. It provides an optimal solution for the

CIDCW (also known as Type 2) and CWD (Type 2.5)

telephone set applications by providing separate input op-

amps for Tip/Ring and 4-wire side (receive pair of the

telephone hybrid or speech IC) connections. The Tip/Ring

connection is compatible with TIA’s MEI scheme and can

be used for FSK demodulation and ‘on hook mode’ CAS

detection. The 4-wire side connection is for ‘off hook

mode’ CAS detection. The CAS detection modes - on

hook and off hook - use different algorithms which are

optimized for the CPE states. In ‘off hook mode’ the CAS

detector is Bellcore compliant when near end speech is

attenuated 8dB or better. ‘On hook mode’ is optimized for

talkdown only and typically meets talkdown condition 1

(the average case) without speech attenuation at Tip/Ring

such as in the on hook state MEI CPE.

Figure 1 - Functional Block Diagram

Anti-Alias

Filter

FSK

Bandpass

FSK

Demod

Data Timing

Recovery

Carrier

Detector

2130Hz

Bandpass

2750Hz

Bandpass

Tone

Detection

Algorithm

GS1en

Mux

DET

Bias

Generator

Oscillator

Control Bit

Decode

FSKen CASen

PWDN

IN1+

IN1-

GS1

IN2+

IN2-

GS2

REF

OSC1 OSC2 CB0 CB2CB1

DATA

DCLK

DR/DET

Vdd

Vss

On/Off Hook mode

MODE

FSKen

CASen

GS1en

PWDN

Patent pending

November 2006

Ordering Information

MT88E46AS 20 Pin SOIC Tubes

MT88E46ASR 20 Pin SOIC Tape & Reel

MT88E46AS1 20 Pin SOIC* Tubes, Bake &

Drypack

MT88E46ASR1 20 Pin SOIC* Tape & Reel,

Bake & Drypack

*Pb Free Matte Tin

-40 to +85 °C

MT88E46 Data Sheet

Change Summary

Changes from March 2000 Issue to November 2006 Issue.

Figure 2 - Pin Connections

Page Item Change

1 Updated Ordering Information.

Pin Description

Pin # Name Description

REF

Voltage Reference (Output). Nominally Vdd/2. It is used to bias the GS1 (Tip/Ring connection) and

GS2 (telephone hybrid or speech IC receive pair connection) input op-amps.

2IN1+GS1 Op-Amp Non-inverting Input. The op-amp is for connecting the MT88E46 to Tip/Ring.

3IN1-GS1 Op-Amp Inverting Input. The op-amp is for connecting the MT88E46 to Tip/Ring.

4GS1

Gain Select 1 (Output). This is the output of the GS1 op-amp. The op-amp should be used to connect the

MT88E46 to Tip and Ring. The Tip/Ring signal can be amplified or attenuated at GS1 via selection of the

feedback resistor between GS1 and IN1-.

FSK demodulation or ‘on hook mode’ CAS detection of the GS1 signal can be selected via the CB1 and

CB2 pins. See Tables 1 and 2.

5VssPower Supply Ground.

6OSC1Oscillator Input. Crystal connection. This pin can also be driven directly from an external clock source.

7OSC2

Oscillator Output. Crystal connection. When OSC1 is driven by an external clock, this pin should be left

open circuit.

8 CB0

Control Bit 0 (CMOS Logic Input). This pin is used primarily to select the 3-wire FSK data interface

mode. When it is low, interface mode 0 is selected where the FSK bit stream is output directly at the

DATA pin. When it is high, interface mode 1 is selected where the FSK byte is stored in a 1 byte buffer

which can be read serially by the application’s microcontroller.

The FSK interface is consisted of the DATA, DCLK and DR

/DET pins. See the 3 pin descriptions to

understand how CB0 affects the FSK interface.

This pin is also used with CB1 and CB2 to put the MT88E46 into a power down state drawing virtually

no power supply current. See Tables 1 and 2.

REF

IN1+

IN1-

GS1

Vss

OSC1

DCLK

DATA

IN2+

IN2-

GS2

CB2

CB1

Vdd

MT88E46

OSC2

CB0

/DET

Data Sheet MT88E46

9DCLK

3-Wire FSK Interface Data Clock (Schmitt Logic Input/CMOS Logic Output). In interface mode 0

(when the CB0 pin is logic low) this is a CMOS output whose rising edge denotes the nominal mid-point

of a bit in the FSK data byte.

In interface mode 1 (when the CB0 pin is logic high) this is a Schmitt trigger input used to shift the FSK

data byte out of an on chip buffer to the DATA pin.

10 DATA

3-Wire FSK Interface Data (CMOS Logic Output). Mark frequency corresponds to logical 1. Space

frequency corresponds to logical 0.

In interface mode 0 (when the CB0 pin is logic low) the FSK serial bit stream is output to DATA directly.

In interface mode 1 (when the CB0 pin is logic high) the start bit is stripped off, the data byte and the

trailing stop bit are stored in a 9 bit buffer. At the end of each word indicated by the DR

signal at the DR/

DET

pin, the microcontroller should shift the byte out to DATA by applying 8 read pulses to the DCLK

pin. A 9th DCLK pulse will shift out the trailing stop bit for framing error checking.

11 DR

/DET

3-Wire FSK Interface Data Ready/CAS Detect (CMOS Logic Output). Active low.

This is a dual purpose pin which indicates the end of an FSK word or the end of CAS.

Data Ready: When FSK demodulation is enabled this pin denotes the end of a word. In both FSK

interface modes 0 and 1, it is normally high and goes low for half a bit time at the end of a word. In mode

1 if DCLK starts while DR

is low, the first rising edge of the DCLK input will return DR to high. This

feature allows an interrupt requested by a low going DR

to be cleared upon reading the first DATA bit.

CAS Detect: When CAS detection is enabled, this pin goes low after the end of CAS for 416 µs

(nominal) to indicate that CAS has been detected.

12 IC Internal Connection. Must be left open circuit.

13 NC No Connection. This pin is not bonded to the die and is unaffected by external connections.

14 CD

Carrier Detect (CMOS Logic Output). Active low.

A logic low indicates that an FSK signal is present. A 10 ms time hysteresis has been provided to allow

for momentary signal discontinuity. The demodulated FSK data is ignored until carrier detect has been

activated.

15 Vdd

Positive Power Supply. A decoupling capacitor should be connected directly across the Vdd and Vss

pins.

16 CB1

Control Bit 1 (CMOS Logic Input). Together with CB2 this pin enables FSK demodulation or CAS

detection. See Tables 1 and 2.

17 CB2

Control Bit 2 (CMOS Logic Input). Together with CB1 this pin enables FSK demodulation or CAS

detection. See Tables 1 and 2.

18 GS2

Gain Select 2 (Output). This is the output of the GS2 op-amp. The op-amp should be used to connect the

MT88E46 to the receive pair of the telephone hybrid or speech IC. The signal can be amplified or

attenuated at GS2 via selection of the feedback resistor between GS2 and IN2-.

When the application is a telephone adjunct box where there is no hybrid or speech IC, if the GS2 gain

with respect to Tip/Ring is to be set to the same as that of GS1, the GS2 op-amp can be connected as a

voltage follower to the GS1 op-amp output (see Figure 5).

The GS2 signal is used for ‘off hook mode’ CAS detection only as selected via the CB1 and CB2 pins.

See Tables 1 and 2.

19 IN2-

GS2 Op-Amp Inverting Input. The op-amp is for connecting the MT88E46 to the receive pair of the

telephone hybrid or speech IC.

20 IN2+

GS2 Op-Amp Non-Inverting Input. The op-amp is for connecting the MT88E46 to the receive pair of

the telephone hybrid or speech IC.

Pin Description

Pin # Name Description

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

MT88E46ASR1

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MT88E46ASR1

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