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MT88E46ASR1

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MT88E46 Data Sheet
16
†AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*Notes:
1. Tip/Ring input signal level.
dBm = decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746Vrms.
dBV = decibels above or below a reference voltage of 1 Vrms. 0dBV = 1 Vrms.
2. GS1 op-amp configured to 0 dB gain for Vdd=5V±10%, -4 dB (preliminary) for Vdd=3V±10%.
3. Both mark and space have the same amplitude.
4. Band limited random noise (300-3400 Hz). Present when FSK signal is present.
†Electrical characteristics are over recommended operating conditions, unless otherwise stated.
AC Electrical Characteristics
†
- FSK Demodulation
Characteristics Sym. Min. Typ.
‡
Max. Units Notes*
1 Accept Signal Level
-40
-37.78
10.0
-
-6.45
-4.23
476
dBV
dBm
mVrms
1, 2
2 Bell 202 Format Reject Signal Level - -
-50.46
-48.24
3
dBV
dBm
mVrms
1, 2, 3
3 Transmission Rate 1188 1200 1212 baud
4
Mark and Space Frequencies
Bell 202 1 (Mark)
Bell 202 0 (Space)
CCITT V.23 1 (Mark)
CCITT V.23 0 (Space)
1188
2178
1280.5
2068.5
1200
2200
1300
2100
1212
2222
1319.5
2131.5
Hz
Hz
Hz
Hz
5 Twist: 20 log (V
MARK
/V
SPACE
)-6-+10dB2
6 Signal to Noise Ratio SNR
FSK
20 - - dB 2, 3, 4
7 Input FSK to CD
low delay t
CP
- - 25 ms See Figures 16, 17
8 Input FSK to CD
high delay t
CA
10 - - ms See Figures 16, 17
9CD
Time Hysteresis 10 - - ms
Electrical Characteristics
†
- Gain Setting Amplifiers
Characteristics Sym. Min. Max. Units Test Conditions
1 Input Leakage Current I
IN
-1µAVss ≤ V
IN
≤ Vdd
2 Input Resistance R
IN
10 - MΩ
3 Input Offset Voltage V
OS
-25mV
4 Power Supply Rejection Ratio PSRR 30 - dB 1kHz ripple on Vdd
5 Common Mode Rejection Ratio CMRR 40 - dB V
CMmin
≤ V
IN
≤ V
CMmax
6 DC Open Loop Voltage Gain A
VOL
40 - dB
7 Unity Gain Bandwidth f
C
0.3 - MHz
8 Output Voltage Swing V
O
0.5 Vdd-0.7 V Load ≥ 100kΩ
9 Capacitive Load (GS1,GS2) C
L
-50pF
10 Resistive Load (GS1,GS2) R
L
100 - kΩ
11 Common Mode Range Voltage V
CM
1.0 Vdd-1.0 V
17
Data Sheet MT88E46
†AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*Notes:
1. OSC1 at 3.579545 MHz ± 0.1%.
2. FSK input data at 1200 ± 12 baud.
3. Function of signal condition.
†AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
†AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics
†
- Mode 0 FSK Data Interface Timing
Characteristics Sym. Min. Typ.
‡
Max. Units Notes*
1
DR
Rise time t
RR
--200ns
into 50 pF load
See Figure 11
2 Fall time t
RF
--200ns
into 50 pF load
See Figure 11
3Low time t
RL
415 416 417 µs
1.
See Figs. 11, 14, 15
4
DATA
Rate 1188 1200 1212 baud 2
5 Input FSK to DATA delay t
IDD
- 1 5 ms See Figure 14
6
DATA
DCLK
Rise time t
R
--200ns
into 50 pF load
See Figure 10
7 Fall time t
F
--200ns
into 50 pF load
See Figure 10
8 DATA to DCLK delay t
DCD
6416-µs
1, 2, 3
See Figure 10
9 DCLK to DATA delay t
CDD
6416-µs
1, 2, 3
See Figure 10
10
DCLK
Frequency f
DCLK0
1201.6 1202.8 1204 Hz 1. See Figure 14
11 High time t
CH
415 416 417 µs 1. See Figures 10, 14
12 Low time t
CL
415 416 417 µs 1. See Figures 10, 14
13
DCLK
DR
DCLK to DR delay t
CRD
415 416 417 µs 1. See Figure 14
AC Electrical Characteristics
†
- Mode 1 FSK Data Interface Timing
Characteristics Sym. Min. Max. Units Notes
1
DCLK
Frequency f
DCLK1
-1MHzSee Figure 15
2 Duty cycle 30 70 %
3 Rise time t
R1
- 100 ns See Figure 12
4
DCLK
DR
DCLK low set up to DR t
DDS
500 - ns See Figure 15
5 DCLK low hold time after DR
t
DDH
500 - ns See Figure 15
AC Electrical Characteristics
†
- General Timing
Characteristics Sym. Min. Max. Units Notes
1
OSC2
Power-up time t
PU
- 50 ms See Figures 16, 17
2 Power-down time t
PD
-10msSee Figure 16
MT88E46 Data Sheet
18
Figure 10 - DATA and DCLK Mode 0 Output Timing
Figure 11 - DR
Output Timing
Figure 12 - DCLK Mode 1 Input Timing
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
Characteristics Sym. Level Units Notes
1 CMOS Threshold Voltage V
CT
0.5*Vdd V
2 Rise/Fall Threshold Voltage High V
HM
0.7*Vdd V
3 Rise/Fall Threshold Voltage Low V
LM
0.3*Vdd V
DATA
DCLK
t
R
t
DCD
t
CDD
t
R
t
F
t
CL
t
CH
t
F
V
HM
V
LM
V
CT
V
HM
V
LM
V
CT
t
RF
t
RR
t
RL
DR
V
HM
V
LM
V
CT
DCLK
t
R1
V
HM
V
LM
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MT88E46ASR1

Mfr. #:
Buy MT88E46ASR1
Manufacturer:
Microchip / Microsemi
Description:
Telecom Interface ICs Pb Free BELLCORE COMPLIANT CNIC2
Lifecycle:
New from this manufacturer.
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