© Semiconductor Components Industries, LLC, 2013
April, 2013 − Rev. 8
1 Publication Order Number:
MC100LVE111/D
MC100LVE111
3.3V ECL 1:9 Differential
Clock Driver
The MC100LVE111 is a low skew 1−to−9 differential driver,
designed with clock distribution in mind. The MC100LVE111’s
function and performance are similar to the popular MC100E111, with
the added feature of low voltage operation. It accepts one signal input,
which can be either differential or single−ended if the V
BB
output is
used. The signal is fanned out to 9 identical differential outputs.
The LVE111 is specifically designed, modeled and produced with
low skew as the key goal. Optimal design and layout serve to minimize
gate to gate skew within a device, and empirical modeling is used to
determine process control limits that ensure consistent t
pd
distributions from lot to lot. The net result is a dependable, guaranteed
low skew device.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50 W, even if
only one side is being used. In most applications, all nine differential
pairs will be used and therefore terminated. In the case where fewer
than nine pairs are used, it is necessary to terminate at least the output
pairs on the same package side as the pair(s) being used on that side, in
order to maintain minimum skew. Failure to do this will result in small
degradations of propagation delay (on the order of 10−20 ps) of the
output(s) being used which, while not being catastrophic to most
designs, will mean a loss of skew margin.
The MC100LVE111, as with most other ECL devices, can be
operated from a positive V
CC
supply in PECL mode. This allows the
LVE111 to be used for high performance clock distribution in +3.3 V
systems. Designers can take advantage of the LVE111’s performance
to distribute low skew clocks across the backplane or the board. In a
PECL environment, series or Thevenin line terminations are typically
used as they require no additional power supplies. For systems
incorporating GTL, parallel termination offers the lowest power by
taking advantage of the 1.2 V supply as a terminating voltage. For
more information on using PECL, designers should refer to
Application Note AN1406/D.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
• 200 ps Part−to−Part Skew
• 50 ps Output−to−Output Skew
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V with V
EE
= −3.0 V to −3.8 V
• Internal Input Pulldown Resistors
• Q Output will Default LOW with Inputs Open or at V
EE
• These are Pb−Free Devices*
MARKING
DIAGRAM*
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
PLCC−28
FN SUFFIX
CASE 776
*For additional marking information, refer to
Application Note AND8002/D.
MC100LVE111G
AWLYYWW
128
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
