MC100LVE111FNR2

MC100LVE111
http://onsemi.com
4
Table 4. LVPECL DC CHARACTERISTICS V
CC
= 3.3 V; V
EE
= 0 V (Note 2)
Symbol
Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
I
EE
Power Supply Current 55 66 55 66 65 78 mA
V
OH
Output HIGH Voltage (Note 3) 2215 2345 2420 2275 2345 2420 2275 2345 2420 mV
V
OL
Output LOW Voltage (Note 3) 1490 1595 1680 1490 1595 1680 1490 1595 1680 mV
V
IH
Input HIGH Voltage (SingleEnded) 2135 2420 2135 2420 2135 2420 mV
V
IL
Input LOW Voltage (SingleEnded) 1490 1825 1490 1825 1490 1825 mV
V
BB
Output Voltage Reference 1.92 2.04 1.92 2.04 1.92 2.04 V
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
1.8 2.9 1.8 2.9 1.8 2.9 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
3. Outputs are terminated through a 50 W resistor to V
CC
2.0 V.
4. V
IHCMR
min varies 1:1 with V
EE
, maximum varies 1:1 with V
CC
. V
IHCMR
is defined as the range within which the V
IH
level may vary, with the
device still meeting the propagation delay specification. The V
IL
level must be such that the peak to peak voltage is less than 1.0 V and greater
than or equal to V
PP
(min).
Table 5. LVNECL DC CHARACTERISTICS V
CC
= 0 V; V
EE
= 3.3 V (Note 5)
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
I
EE
Power Supply Current 55 66 55 66 65 78 mA
V
OH
Output HIGH Voltage (Note 6) 1085 955 880 1025 955 880 1025 955 880 mV
V
OL
Output LOW Voltage (Note 6) 1810 1705 1620 1810 1705 1620 1810 1705 1620 mV
V
IH
Input HIGH Voltage (SingleEnded) 1165 880 1165 880 1165 880 mV
V
IL
Input LOW Voltage (SingleEnded) 1810 1475 1810 1475 1810 1475 mV
V
BB
Output Voltage Reference 1.38 1.26 1.38 1.26 1.38 1.26 V
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
1.5 0.4 1.5 0.4 1.5 0.4 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
6. Outputs are terminated through a 50 W resistor to V
CC
2.0 V.
7. V
IHCMR
min varies 1:1 with V
EE
, maximum varies 1:1 with V
CC
. V
IHCMR
is defined as the range within which the V
IH
level may vary, with the
device still meeting the propagation delay specification. The V
IL
level must be such that the peak to peak voltage is less than 1.0 V and greater
than or equal to V
PP
(min).
MC100LVE111
http://onsemi.com
5
Table 6. AC CHARACTERISTICS V
CC
= 3.3 V; V
EE
= 0 V or V
CC
= 0 V; V
EE
= 3.3 V (Note 8)
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
f
max
Maximum Toggle Frequency > 1.5 > 1.5 > 1.5 GHz
t
PLH
t
PHL
Propagation Delay to Output
IN (Differential Configuration) (Note 9)
sIN (SingleEnded) (Note 10)
400
350
650
700
440
390
630
680
445
395
635
685
ps
t
skew
WithinDevice Skew (Note 11)
ParttoPart Skew
(Differential Configuration)
50
250
50
200
50
200
ps
t
JITTER
CycletoCycle Jitter 0.2 < 1 0.2 < 1 0.2 < 1 ps
V
PP
Input Swing (Note 12) 500 1000 500 1000 500 1000 mV
t
r
/t
f
Output Rise/Fall Time (20%80%) 200 600 200 600 200 600 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. V
EE
can vary ±0.3 V.
9. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
10.The singleended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
11. The withindevice skew is defined as the worst case difference between any two similar delay paths within a single device.
12.V
PP
(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The V
PP
(min) is AC limited
for the E111 as a differential input as low as 50 mV will still produce full ECL levels at the output.
0
100
200
300
400
500
600
700
800
900
0 300 600 900 1200 1500 1800 2100 2400
1
2
3
4
5
6
7
8
9
Figure 3. F
max
/Jitter
FREQUENCY (MHz)
(JITTER)
V
OUTpp
(mV)
JITTER
OUT
ps (RMS)
MC100LVE111
http://onsemi.com
6
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50 W
Z
o
= 50 W
50 W 50 W
V
TT
V
TT
= V
CC
2.0 V
ORDERING INFORMATION
Device Package Shipping
MC100LVE111FNG PLCC28
(PbFree)
37 Units / Rail
MC100LVE111FNR2G PLCC28
(PbFree)
500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices

MC100LVE111FNR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V ECL 1:9 DIFF
Lifecycle:
New from this manufacturer.
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