LTC3735
13
3735fa
APPLICATIONS INFORMATION
In a 2-phase converter, the net ripple current seen by
the output capacitor is much smaller than the individual
inductor ripple currents due to ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Linear Technology Application Note 77.
Figure 3 shows the net ripple current seen by the output
capacitors for 1- and 2-phase configurations. The output
ripple current is plotted for a fixed output voltage as the
duty factor is varied between 10% and 90% on the x-axis.
The graph can be used in place of tedious calculations,
simplifying the design process.
Accepting larger values of ∆I
L
allows the use of low in-
ductances, but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
∆I
L
= 0.4(I
OUT
)/2, where I
OUT
is the total load current.
Remember, the maximum ∆I
L
occurs at the maximum
input voltage. The individual inductor ripple currents
are determined by the frequency, inductance, input and
output voltages.
is very dependent on inductor type selected. As inductance
increases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore cop-
per losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
A variety of inductors designed for high current, low volt-
age applications are available from manufacturers such
as Sumida, Coilcraft, Coiltronics, Toko and Panasonic.
Power MOSFET, D1 and D2 Selection
Two external power MOSFETs must be selected for each
output stage with the LTC3735: one N-channel MOSFET
for the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the PV
CC
volt-
age. This voltage typically ranges from 4.5V to 7V
. Con-
sequently, logic-level threshold MOSFETs must be used
in most applications. Pay close attention to the BV
DSS
specification for the MOSFETs as well; most of the logic-
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R
DS(ON)
, gate charge Q
G
, reverse transfer ca-
pacitance C
RSS
, breakdown voltage BV
DSS
and maximum
continuous drain current I
D(MAX)
.
When the LTC3735 is operating at continuous mode in a
step-down configuration, the duty cycles for the top and
bottom MOSFETs of each power stage are approximately:
Top MOSFET Duty Cycle =
V
OUT
V
IN
(1)
Bottom MOSFET Duty Cycle =
V
IN
V
OUT
V
IN
(2)
Figure 3. Normalized Output Ripple Current
vs Duty Factor [I
RMS
≈ 0.3 (∆I
O(P-P)
]
DUTY FACTOR (V
OUT
/V
IN
)
0.1 0.2 0.3 0.4
0.5 0.6 0.7 0.8 0.9
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3735 F03
2-PHASE
1-PHASE
∆I
O(P-P)
V
O
/fL
Inductor Core Selection
Once the values for L1 and L2 are known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ cores. Actual core loss
is independent of core size for a fixed inductor value, but it
LTC3735
14
3735fa
APPLICATIONS INFORMATION
The conduction losses of the top and bottom MOSFETs
are therefore:
P
CONTOP
=
V
OUT
V
IN
I
OUT
2
2
1+ δ T
( )
R
DS(ON)
(3)
P
CONBOT
=
V
IN
V
OUT
V
IN
I
OUT
2
2
1+ δ T
( )
(4)
R
DS(ON)
where I
OUT
is the total output current at full load, ∆T is the
difference between MOSFET operating temperature and
room temperature, and δ is the temperature dependency
of R
DS(ON)
. δ is roughly 0.004/°C ~ 0.006/°C for low volt-
age MOSFETs.
The power losses of driving the top and bottom MOSFETs
are simply:
P
DRTOP
= Q
G
• PV
CC
• f (5)
P
DRBOT
= Q
G
• PV
CC
• f (6)
Use Q
G
data at V
GS
= PV
CC
in MOSFET data sheets. f is
the switching frequency as described previously. Please
notice that the above gate driving losses are usually not
dissipated by the MOSFETs. Instead they are mainly dis-
sipated on the internal drivers of the LTC3735, if there are
no resistors connected between the drive pins (TG, BG)
and the gates of the MOSFETs.
The calculation of MOSFET switching loss is complicated
by several factors including the wide distribution of power
MOSFET threshold voltage, the nonlinearity of current ris-
ing/falling characteristic and the Miller Effect. Given the
data in a typical power MOSFET data sheet, the switch-
ing losses of the top and bottom MOSFETs can only be
estimated as follows:
P
SWTOP
=
V
IN
2
I
OUT
4
f C
RSS
R
DR
per Phase
1
V
DR
V
TH(MIN)
+
1
V
TH(MIN)
(7)
P
SWBOT
≈ 0 (8)
where R
DR
is the effective driver resistance (of approxi-
mately 2Ω), V
DR
is the driving voltage (= PV
CC
) and V
TH(MIN)
is the minimum gate threshold voltage of the MOSFET.
Please notice that the switching loss of the bottom MOSFET
is effectively negligible because the current conduction of
the antiparalleling diode. This effect is often referred as
zero-voltage-transition (ZVT). Similarly when the LTC3735
converter works under fully synchronous mode at light
load, the reverse inductor current can also go through
the body diode of the top MOSFET and make the turn-on
loss to be negligible. However, equations 7 and 8 have to
be used in calculating the worst-case power loss, which
happens at highest load level.
The selection criteria of power MOSFETs start with the
stress check:
V
IN
< BV
DSS
I
MAX
< I
D(MAX)
and
P
CONTOP
+ P
SWTOP
< top MOSFET maximum power
dissipation specification
P
CONBOT
+ P
SWBOT
< bottom MOSFET maximum power
dissipation specification
The maximum power dissipation allowed for each MOSFET
depends heavily on MOSFET manufacturing and pack-
aging, PCB layout and power supply cooling method.
Maximum power dissipation data are usually specified
in MOSFET data sheets under different PCB mounting
conditions.
The next step of selecting power MOSFETs is to minimize
the overall power loss:
P
OVL
= P
TOP
+ P
BOT
= (P
CONTOP
+ P
DRTOP
+ P
SWTOP
) + (P
CONBOT
+
P
DRBOT
+ P
SWBOT
)
For typical mobile CPU applications where the ratio between
input and output voltages is higher than 2:1, the bottom
MOSFET conducts load current most of the time while
the main losses of the top MOSFET are for switching and
driving. Therefore a low R
DS(ON)
part (or multiple parts in
parallel) would minimize the conduction loss of the bottom
LTC3735
15
3735fa
APPLICATIONS INFORMATION
MOSFET while a higher R
DS(ON)
but lower Q
G
and C
RSS
part would be desirable for the top MOSFET.
The Schottky diodes, D1 and D2 in Figure 1 conduct dur-
ing the dead-time between the conduction of the top and
bottom MOSFETs. This helps reduce the current flowing
through the body diode of the bottom MOSFET. A body
diode usually has a forward conduction voltage higher than
that of a Schottky and is thus detrimental to efficiency. The
charge storage and reverse recovery of a body diode also
cause high frequency rings at the switching nodes (the
conjunction nodes between the top and bottom MOSFETs),
which are again not desired for efficiency or EMI. Some
power MOSFET manufacturers integrate a Schottky diode
with a power MOSFET, eliminating the need to parallel an
external Schottky. These integrated Schottky-MOSFETs,
however, have smaller MOSFET die sizes than conventional
parts and are thus not suitable for high current applications.
C
IN
and C
OUT
Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V
OUT
/
V
IN
. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a closed form
equation can be found in Linear Technology Application
Note 77. Figure 4 shows the input capacitor ripple current
for a 2-phase configuration with the output voltage fixed
and input voltage varied. The input ripple current is nor-
malized against the DC output current. The graph can be
used in place of tedious calculations. The minimum input
ripple current can be achieved when the input voltage is
twice the output voltage.
In the graph of Figure 4, the 2-phase local maximum input
RMS capacitor currents are reached when:
V
OUT
V
IN
=
2k 1
4
where k = 1, 2
These worst-case conditions are commonly used for
design, considering input/output variations and long
term reliability. Note that capacitor manufacturers ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor,
or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paral-
leled to meet size or height requirements in the design.
Always consult the capacitor manufacturer if there is any
question.
DUTY FACTOR (V
OUT
/V
IN
)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0.9
0.6
0.5
0.4
0.3
0.2
0.1
0
3735 F04
RMS INPUT RIPPLE CURRNET
DC LOAD CURRENT
2-PHASE
1-PHASE
Figure 4. Normalized RMS Input Ripple Current
vs Duty Factor for 1 and 2 Output Stages
It is important to note that the efficiency loss is propor-
tional to the input RMS current squared and therefore a
2-phase implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the reduc-
tion of the input ripple current in a 2-phase system. The
required amount of input capacitance is further reduced
by the factor, 2, due to the reduction in input RMS current.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment has been met, the RMS current rating generally far
exceeds the I
RIPPLE(P-P)
requirements. The steady state
output ripple (∆V
OUT
) is determined by:
V
OUT
I
RIPPLE
ESR+
1
16 f C
OUT
where f = operating frequency of each stage, C
OUT
=
output capacitance and ∆I
RIPPLE
= interleaved inductor
ripple currents.
∆I
RIPPLE
can be calculated from the duty factor and the
∆I
L
of each stage. A closed form equation can be found in

LTC3735EG#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2-Phase IMVP4 Controller
Lifecycle:
New from this manufacturer.
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