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LTC3735EG#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
LTC3735
22
3735fa
APPLICATIONS INFORMATION
Rewriting this equation, we can estimate the R
AVP
value
to be:
R
AVP≅
35.5•R3
m •| AVP|
R
SENSE
–1
(12)
Typically the calculation results based on these equations
have ±10% tolerance. So the resistor values need to be
fine tuned.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3735 circuits: 1) I
2
R losses, 2) Topside
MOSFET transition losses, 3) PV
CC
supply current and
4) C
IN
loss.
1) I
2
R losses are predicted from the DC resistances of
the fuse (if used), MOSFET, inductor, and current sense
resistor. In continuous mode the average output current
flows through L and R
SENSE
, but is “chopped” between the
topside MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same R
DS(ON)
, then the
resistance of one MOSFET can simply be summed with
the resistances of L, R
SENSE
and ESR to obtain I
2
R losses.
For example, if each R
DS(ON)
= 10mΩ, R
L
= 10mΩ, and
R
SENSE
= 5mΩ, then the total resistance is 25mΩ. This
results in losses ranging from 2% to 8% as the output
current increases from 3A to 15A per output stage for a 5V
output, or a 3% to 12% loss per output stage for a 3.3V
output. Efficiency varies as the inverse square of V
OUT
for
the same external components and output power level.
The combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
2) Transition losses apply only to the topside MOSFET(s),
and are significant only when operating at high input volt-
ages (typically 12V or greater). Transition losses can be
estimated from:
Transition Loss =
V
IN
2
•I
OUT
4
• f • C
RSS
•R
DR
•
1
V
DR
– V
TH(MIN)
+
1
V
TH(MIN)
per Phase
3) PV
CC
drives both top and bottom MOSFETs. The MOSFET
driver current results from switching the gate capacitance
of the power MOSFETs. Each time a MOSFET gate is
switched from low to high to low again, a packet of charge
dQ moves from PV
CC
to ground. The resulting dQ/dt is a
current out of PV
CC
that is typically much larger than the
control circuit current. In continuous mode, I
GATECHG
=
(Q
T
+ Q
B
)f, where Q
T
and Q
B
are the gate charges of the
topside and bottom side MOSFETs and f is the switching
frequency.
4) The input capacitor has the difficult job of filtering
the large RMS input current to the regulator. It must
have a very low ESR to minimize the AC I
2
R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
The LTC3735 2-phase architecture typically halves the
input and output capacitor requirements over 1-phase
solutions.
Other losses, including C
OUT
ESR loss, Schottky diode
conduction loss during dead time, inductor core loss and
internal control circuitry supply current generally account
for less than 2% additional loss.
Checking Transient Response
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
LTC3735
23
3735fa
APPLICATIONS INFORMATION
load current. When a load step occurs, V
OUT
shifts by an
amount equal to ∆I
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recovery
time V
OUT
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the I
TH
pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The I
TH
external components shown
in the Figure 1 circuit will provide an adequate starting
point for most applications.
The I
TH
series R
C
-C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon first because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of <1µs will
produce output voltage and I
TH
pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. The initial output voltage step result-
ing from the step change in output current may not be
within
the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why
it is better to look at the I
TH
pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased
by increasing R
C
and the bandwidth of the loop will be
increased by decreasing C
C
. If R
C
is increased by the
same factor that C
C
is decreased, the zero frequency will
be kept the same, thereby keeping the phase the same in
the most critical frequency range of the feedback loop.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main battery line in an automobile
is the source of a number of nasty potential transients,
including load-dump, reverse-battery and double-battery.
Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alterna-
tor can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 10 is the most straightfor-
ward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse-battery,
while the transient suppressor clamps the input voltage
during load-dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of
the converter. Although the LT3735 has a maximum input
voltage of 32V, most applications will be limited to 30V
by the MOSFET BV
DSS
.
+
LTC3735
PV
CC
PV
CC
V
BAT
12V
3735 F10
Figure 10. Automotive Application Protection
LTC3735
24
3735fa
APPLICATIONS INFORMATION
Design Example
As a design example, assume V
IN
= 12V (nominal), V
IN
= 21V (max), V
OUT
= 1.5V, I
MAX
= 35A, and f = 350kHz
(each phase).
The inductance value is chosen first based on a 40% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. The minimum
inductance for 40% ripple current is:
L ≥
V
OUT
f • ∆I
• 1–
V
OUT
V
IN
=
1.5V
350kHz • 40%•17.5A
( )
•
1–
1.5V
21V
= 0.57µH
Using L = 0.6µH, a common “off-the-shelf” value results
in 38%ripple current. The peak inductor current will be
the maximum DC current plus one half of the ripple cur-
rent, or 21A.
Tie the FREQSET pin to 1.2V, resistively divided down from
PV
CC
to have 350kHz operation for each phase.
The minimum on-time also occurs at maximum input
voltage:
t
ON(MIN)
=
V
OUT
V
IN
• f
=
1.5V
21V • 350kHz
= 204ns
which is larger than 150ns, the typical minimum on time
of the LTC3735.
R
SENSE1
and R
SENSE2
can be calculated by using a con-
servative maximum sense voltage threshold of 40mV and
taking into account of the peak current:
R
SENSE
=
40mV
21A
= 0.002Ω
The power loss dissipated by the top MOSFET can be cal-
culated with equations 3 and 7. Using a Fairchild FDS7760
as an example: R
DS(ON)
= 8mΩ, Q
G
= 55nC at 5V V
GS
, C
RSS
= 307pF, V
TH(MIN)
= 1V. At maximum input voltage with
T
J
(estimated) = 85°C at an elevated ambient temperature:
P
TOP
=
1.5V
21V
•
35A
2
2
• 1+ 0.005 • 85°C – 25°C
( )
( )
•
0.008Ω +
21V
2
•17.5A
2
• 350kHz • 307pF •
2Ω •
1
5V – 1V
+
1
1V
= 1.26W
Equation 4 gives the worst-case power loss dissipated
by the bottom MOSFET (assuming FDS7760 and T
J
=
85°C again):
P
BOT
=
21V – 1.5V
21V
•
35A
2
2
•
1+ 0.005 • 85°C – 25°C
( )
( )
• 0.008Ω
= 2.95W
Therefore it is necessary to have two FDS7760s in parallel
to split the power loss.
A short-circuit to ground will result in a folded back cur-
rent of about:
I
SC
=
25mV
0.002Ω
+
1
2
•
200ns • 21V
0.6µH
= 16A
The worst-case power dissipation by the bottom MOSFET
under short-circuit conditions is:
P
BOT
=
1
350kHz
– 200ns
1
350kHz
• 16A
( )
2
•
1+ 0.005 • 85°C – 25°C
( )
( )
• 0.008Ω
=
2.48W
which is less than normal, full load conditions.
The nominal duty cycle of this application is equation 1:
DC =
1.5V
12V
= 12.5%
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LTC3735EG#PBF

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Buy LTC3735EG#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2-Phase IMVP4 Controller
Lifecycle:
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