LTC3735
10
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OPERATION
(Refer to Functional Diagram)
Main Control Loop
The LTC3735 uses a constant frequency, current mode step-
down architecture with the two output stages operating
180 degrees out of phase. During normal operation, each
top MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current
comparator, I
1
, resets the RS latch. The peak inductor
current at which I
1
resets the RS latch is controlled by
the voltage on the I
TH
pin, which is the output of error
amplifier EA. The V
OA
+
pin receives the voltage feedback
signal, which is compared to the internal reference voltage
by the EA. When the load current increases, it causes a
slight decrease in EA inverting input node
relative to the
0.6V reference, which in turn causes the I
TH
voltage to
increase until the average inductor current matches the
new load current. After the top MOSFET has turned off,
the bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara-
tor I
2
, or the beginning of the next cycle.
The top MOSFET drivers are biased from floating bootstrap
capacitor C
B
, which normally is recharged during each off
cycle through an external diode when the top MOSFET
turns off. As V
IN
decreases to a voltage close to V
OUT
,
the loop may enter dropout and attempt to turn on the
top MOSFET continuously. The dropout detector detects
this and forces the top MOSFET off for about 500ns every
sixth cycle to allow C
B
to recharge.
The main control loop is shut down by pulling the RUN/
SS pin low. Releasing RUN/SS allows an internal 1.5µA
current source to charge soft-start capacitor C
SS
. When
C
SS
reaches 1.5V, the main control loop is enabled with
the internal I
TH
voltage clamped at approximately 30%
of its maximum value. As C
SS
continues to charge, the
internal I
TH
voltage is gradually released allowing normal,
full-current operation.
Frequency Programming and Antiphase Operation
The switching frequency of the LTC3735 is determined by
the DC voltage at the FREQSET pin. A DC voltage ranging
from 0V to 2.4V moves the internal oscillator frequency
from 210kHz to 550kHz.
This frequency is the actual switching frequency of either
channel. Because the two channels operate 180°C out of
phase, the apparent frequency at both V
IN
and V
OUT
is
twice the actual switching frequency, minimizing ripple
voltages and speeding up transient responses.
Low Current Operation (PSIB)
The PSIB pin selects between two modes of operation.
When PSIB is above 0.6V, both channels operate in full
synchronous switching mode. Both bottom drivers (BG1,
BG2) are kept on once they are turned on until their re-
spective oscillator sets the RS latch. The inductor current
can therefore go from output back to input power supply
and could potentially boost the input supply to dangerous
voltage levels—BEWARE! This mode of operation is also
of lower efficiency, given both channels are fully enabled
and much current can circulate between input and output.
However, this mode provides faster transient response,
lower input noise and minimum output ripple.
When PSIB is below 0.6V, the bottom drivers (BG1, BG2)
are turned off if the inductor current starts to reverse. This
mode of operation prevents current going from output
back to input and eliminates the conduction power loss
related to circulating current. If the DPRSLPVR signal
goes high in this mode, Channel 2 will be shut off and
only Channel 1 will be active in supplying load current.
This further eliminates power MOSFET gate driving and
transition losses of Channel 2. Since DPRSLPVR indicates
the entry to deeper sleep state, this “channel shedding”
technique optimizes the voltage regulator efficiency at
light loads. Table 1 summarizes the operation modes for
different pin configurations.
Table 1. Low Current Operation Modes
PSIB DPRSLPVR OPERATION MODE
High High or Low Both Channels ON, Fully Synchronous
Switching, Inductor Current is Allowed to
Reverse
Low Low Both Channels ON; Reverse Current is
Prevented
Low High Channel 2 is Shut Off, Reverse Current is
Prevented
LTC3735
11
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OPERATION
(Refer to Functional Diagram)
Output Voltage at Start-Up and at Deeper Sleep State
Under normal conditions, the output voltage of the regula-
tor is commanded by six VID bits, except at start-up and
at deeper sleep state. At start-up, the RUN/SS capacitor
starts to charge up and its voltage limits the inrush current
from the input power source. This linearly rising current
limit provides a controlled output voltage rise. During
start-up, the VID command is ignored and the output set
point is determined by the value of the resistor connected
to the RBOOT pin. The VID bits continue to be ignored for
15 switching cycles after the completion of the following
two conditions: 1) output voltage has risen up and has
regulated 2) MCH_PG signal has asserted. After 15 switch-
ing cycles, output voltage is fully commanded by VID bits.
In deeper sleep state, the VID command and STP_CPUB
signal are ignored and the output set point is determined
by the parallel value of the resistors at the RDPRSLP pin
and RDPSLP pin.
Operational Amplifier and Deep Sleep Offset
The internal operational amplifier provides a programmable
output offset at deep sleep state (when the STP_CPUB
signal is low). The offset percentage is programmed by
the resistor from RDPSLP to V
OA
+
and the resistor from
output to V
OA
+
. The amplifier has an output slew rate of
5V/µs and is capable of driving capacitive loads with an
output RMS current typically up to 40mA. The open-loop
gain of the amplifier is >120dB and the unity-gain band-
width is 2MHz.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good
The PGOOD pin is connected to the drain of an internal
N-channel MOSFET. The MOSFET turns on when the out-
put voltage is not within ±10% of its nominal set point.
When the output voltage is within ±10% of its nominal set
point, the MOSFET turns off and PGOOD is high imped-
ance. PGOOD monitors the V
BOOT
voltage when MCH_PG
is not asserted. During VID, deep sleep or deeper sleep
transitions, PGOOD is masked from going low for 110µs,
preventing the system from resetting during CPU mode
changes. When VID bits, STP_CPUB or DPRSLPVR signals
change again after a previous transition, but before the
timer expires, the internal timer resets.
Short-Circuit Detection
The RUN/SS capacitor is used initially to limit the in-
rush current from the input power source. Once the
controllers have been given time, as determined by the
capacitor on the RUN/SS pin, to charge up the output
capacitors and provide full-load current, the RUN/SS
capacitor is then used as a short-circuit timeout circuit.
If the output voltage falls to less than 70% of its nominal
output voltage the RUN/SS capacitor begins discharg-
ing assuming that the output is in a severe overcurrent
and/or short-circuit condition. If the condition lasts for
a long enough period as determined by the size of the
RUN/SS capacitor, the controller will be shut down until the
RUN/SS pin voltage is recycled. This built-in latchoff can
be overidden by providing a current >5µA to the RUN/SS
pin. This current shortens the soft-start period but also
prevents net discharge of the RUN/SS capacitor during a
severe overcurrent and/or short-circuit condition. Foldback
current limiting is activated when the output voltage falls
below 70% of its nominal level whether or not the short-
circuit latchoff circuit is enabled.
LTC3735
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APPLICATIONS INFORMATION
The basic LTC3735 application circuit is shown in
Figure1 on the first page of this data sheet. External com-
ponent selection begins with the selection of the inductors
based on ripple current requirements and continues with
the current sensing resistors using the calculated peak
inductor current and/or maximum current limit. Next, the
power MOSFETs, D1 and D2 are selected. The operating
frequency and the inductor are chosen based mainly on
the amount of ripple current. Finally, C
IN
is selected for its
ability to handle the input ripple current (that PolyPhase
®
operation minimizes) and C
OUT
is chosen with low enough
ESR to meet the output ripple voltage and load step
specifications (also minimized with PolyPhase). Current
mode architecture provides inherent current sharing be-
tween output stages. The circuit shown in Figure1 can
be configured for operation up to an input voltage of 28V
(limited by the external MOSFETs). Current mode control
allows the ability to connect the two output stages to two
different input power supply rails. A heavy output load
can take some power from each input supply according
to the selection of the R
SENSE
resistors.
R
SENSE
Selection For Output Current
R
SENSE1,2
are chosen based on the required peak output
current. The LTC3735 current comparator has a maximum
threshold of 72mV/R
SENSE
and an input common mode
range of SGND to PV
CC
. The current comparator threshold
sets the peak inductor current, yielding a maximum aver-
age output current I
MAX
equal to the peak value less half
the peak-to-peak ripple current, ∆I
L
.
Assuming a common input power source for each out-
put stage and allowing a margin for variations in the
LTC3735 and external component values yields:
R
SENSE
= 2(40mV/I
MAX
)
Operating Frequency
The LTC3735 uses a constant frequency architecture with
the frequency determined by an internal capacitor. This
capacitor is charged by a fixed current plus an additional
current which is proportional to the DC voltage applied
to the FREQSET pin. The FREQSET voltage is internally
set to 1.2V. It is recommended that this pin is actively
biased with a resistor divider to prevent noise getting
into the system.
A graph for the voltage applied to the FREQSET pin vs fre-
quency is given in Figure2. As the operating frequency is
increased the gate drive and switching losses will be higher,
reducing efficiency (see Efficiency Considerations). The
maximum switching frequency is approximately 550kHz.
OPERATING FREQUENCY (kHz)
600
550
500
450
400
350
300
250
200
150
100
0 0.5 1.0 1.5 2.0 3.02.5
FREQSET PIN VOLTAGE (V)
3735 F02
Figure 2. Operating Frequency vs V
FREQSET
Inductor Value Calculation and Output Ripple Current
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
MOSFET gate charge and transition losses increase
directly with frequency. In addition to this basic tradeoff,
the effect of inductor value on ripple current and low cur-
rent operation must also be considered. The PolyPhase
approach reduces both input and output ripple currents
while optimizing individual output stages to run at a lower
fundamental frequency, enhancing efficiency.
The inductor value has a direct effect on ripple current.
The inductor ripple current ∆I
L
, decreases with higher
inductance or frequency and increases with higher V
IN
:
I
L
=
V
OUT
fL
1
V
OUT
V
IN
where f is the individual output stage operating frequency.

LTC3735EUHF#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators LTC3735 in QFN Package
Lifecycle:
New from this manufacturer.
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