HI5662/6IN Datasheet HI5662/6IN | P13-P14

3-13

or below AGND. In this case, V

could range between 0.5V

and 4.5V without a significant change in ADC performance.

The simplest way to produce V

is to use the DC bias source,

I/QV

, of the HI5662.

The single ended analog input can be DC coupled

(Figure 18) as long as the input is within the analog input

common mode voltage range.

The resistor, R, in Figure 18 is not absolutely necessary but

may be used as a load setting resistor. A capacitor, C,

connected from I/Q

+ to I/Q

- will help ﬁlter any high

frequency noise on the inputs, also improving performance.

Values around 20pF are sufﬁcient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must take into account the highest

frequency component of the analog input signal.

A single ended source may give better overall system

performance if it is ﬁrst converted to differential before

driving the HI5662.

Sampling Clock Requirements

The HI5662 sampling clock input provides a standard high-

speed interface to external TTL/CMOS logic families.

In order to ensure rated performance of the HI5662, the duty

cycle of the clock should be held at 50% ±5%. It must also

have low jitter and operate at standard TTL/CMOS levels.

Performance of the HI5662 will only be guaranteed at

conversion rates above 1MSPS (Typ). This ensures proper

performance of the internal dynamic circuits. Similarly, when

power is ﬁrst applied to the converter, a maximum of 20

cycles at a sample rate above 1MSPS must to be performed

before valid data is available.

Supply and Ground Considerations

The HI5662 has separate analog and digital supply and ground

pins to keep digital noise out of the analog signal path. The

digital data outputs also have a separate supply pin, DV

CC3

which can be powered from a 3.0V or 5.0V supply. This allows

the outputs to interface with 3.0V logic if so desired.

The part should be mounted on a board that provides

separate low impedance connections for the analog and

digital supplies and grounds. For best performance, the

supplies to the HI5662 should be driven by clean, linear

regulated supplies. The board should also have good high

frequency decoupling capacitors mounted as close as

possible to the converter. If the part is powered off a single

supply then the analog supply can be isolated by a ferrite

bead from the digital supply.

Refer to the application note “Using Intersil High Speed A/D

Converters” (AN9214) for additional considerations when

using high speed converters.

Static Performance Deﬁnitions

Offset Error (V

)

The midscale code transition should occur at a level

LSB

above half-scale. Offset is deﬁned as the deviation of the

actual code transition from this point.

Full-Scale Error (FSE)

The last code transition should occur for an analog input that

LSB below Positive Full Scale (+FS) with the offset

error removed. Full scale error is deﬁned as the deviation of

the actual code transition from this point.

Differential Linearity Error (DNL)

DNL is the worst case deviation of a code width from the

ideal value of 1LSB.

Integral Linearity Error (INL)

INL is the worst case deviation of a code center from a best

ﬁt straight line calculated from the measured data.

Power Supply Sensitivity

Each of the power supplies are moved plus and minus 5% and

the shift in the offset and full scale error (in LSBs) is noted.

Dynamic Performance Deﬁnitions

Fast Fourier Transform (FFT) techniques are used to evaluate

the dynamic performance of the HI5662. A low distortion sine

wave is applied to the input, it is coherently sampled, and the

output is stored in RAM. The data is then transformed into the

frequency domain with an FFT and analyzed to evaluate the

dynamic performance of the A/D. The sine wave input to the

part is typically -0.5dB down from full scale for all these tests.

SNR and SINAD are quoted in dB. The distortion numbers are

quoted in dBc (decibels with respect to carrier) and DO NOT

include any correction factors for normalizing to full scale.

The Effective Number of Bits (ENOB) is calculated from the

SINAD data by:

ENOB = (SINAD - 1.76 + V

CORR

) / 6.02,

where: V

CORR

= 0.5dB (Typical).

CORR

adjusts the SINAD, and hence the ENOB, for the

amount the analog input signal is backed off from full scale.

I/Q

HI5662

FIGURE 18. DC COUPLED SINGLE ENDED INPUT

HI5662

3-14

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Signal To Noise and Distortion Ratio (SINAD)

SINAD is the ratio of the measured RMS signal to RMS sum

of all the other spectral components below the Nyquist

frequency, f

/2, excluding DC.

Signal To Noise Ratio (SNR)

SNR is the ratio of the measured RMS signal to RMS noise at

a speciﬁed input and sampling frequency. The noise is the

RMS sum of all of the spectral components below f

excluding the fundamental, the ﬁrst ﬁve harmonics and DC.

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first 5 harmonic

components to the RMS value of the fundamental input signal.

2nd and 3rd Harmonic Distortion

This is the ratio of the RMS value of the applicable harmonic

component to the RMS value of the fundamental input signal.

Spurious Free Dynamic Range (SFDR)

SFDR is the ratio of the fundamental RMS amplitude to the

RMS amplitude of the next largest spectral component in the

spectrum below f

/2.

Intermodulation Distortion (IMD)

Nonlinearities in the signal path will tend to generate

intermodulation products when two tones, f

and f

, are

present at the inputs. The ratio of the measured signal to the

distortion terms is calculated. The terms included in the

calculation are (f

), (f

-f

), (2f

-f

+2f

), (f

-2f

). The ADC is tested with each tone 6dB

below full scale.

Transient Response

Transient response is measured by providing a full-scale

transition to the analog input of the ADC and measuring the

number of cycles it takes for the output code to settle within

10-bit accuracy.

Over-Voltage Recovery

Over-Voltage Recovery is measured by providing a full-scale

transition to the analog input of the ADC which overdrives

the input by 200mV, and measuring the number of cycles it

takes for the output code to settle within 10-bit accuracy.

Full Power Input Bandwidth (FPBW)

Full power input bandwidth is the analog input frequency at

which the amplitude of the digitally reconstructed output has

decreased 3dB below the amplitude of the input sine wave.

The input sine wave has an amplitude which swings from

-FS to +FS. The bandwidth given is measured at the

speciﬁed sampling frequency.

I/Q Channel Crosstalk

I/Q Channel Crosstalk is a measure of the amount of

channel separation or isolation between the two A/D

converter cores contained within the dual converter

package. The measurement consists of stimulating one

channel of the converter with a fullscale input signal and

then measuring the amount that signal is below, in dBc, a

fullscale signal on the opposite channel.

Timing Deﬁnitions

Refer to Figure 1 and Figure 2 for these deﬁnitions.

Aperture Delay (t

)

Aperture delay is the time delay between the external

sample command (the falling edge of the clock) and the time

at which the signal is actually sampled. This delay is due to

internal clock path propagation delays.

Aperture Jitter (t

)

Aperture jitter is the RMS variation in the aperture delay due

to variation of internal clock path delays.

Data Hold Time (t

)

Data hold time is the time to where the previous data (N - 1)

is no longer valid.

Data Output Delay Time (t

)

Data output delay time is the time to where the new data (N)

is valid.

Data Latency (t

LAT

)

After the analog sample is taken, the digital data

representing an analog input sample is output to the digital

data bus following the 6th cycle of the clock after the analog

sample is taken. This is due to the pipeline nature of the

converter where the analog sample has to ripple through the

internal subconverter stages. This delay is speciﬁed as the

data latency. After the data latency time, the digital data

representing each succeeding analog sample is output

during the following clock cycle. The digital data lags the

analog input sample by 6 sample clock cycles.

Power-Up Initialization

This time is deﬁned as the maximum number of clock cycles

that are required to initialize the converter at power-up. The

requirement arises from the need to initialize the dynamic

circuits within the converter.

HI5662

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

HI5662/6IN

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