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HI5662/6IN

P1-P3P4-P6P7-P9P10-P12P13-P14
3-7
Data Output Delay, t
OD
- 11.7 - ns
Data Latency, t
LAT
For a Valid Sample (Note 2) 6 6 6 Cycles
Power-Up Initialization Data Invalid Time (Note 2) - - 20 Cycles
Sample Clock Pulse Width (Low) (Note 2) 7.5 8.3 - ns
Sample Clock Pulse Width (High) (Note 2) 7.5 8.3 - ns
Sample Clock Duty Cycle Variation ±5%
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AV
CC
(Note 2) 4.75 5.0 5.25 V
Digital Supply Voltage, DV
CC1
and DV
CC2
(Note 2) 4.75 5.0 5.25 V
Digital Output Supply Voltage, DV
CC3
At 3.0V (Note 2) 2.7 3.0 3.3 V
At 5.0V (Note 2) 4.75 5.0 5.25 V
Supply Current, I
CC
f
S
= 60MSPS - 130 - mA
Power Dissipation - 650 670 mW
Offset Error Sensitivity, ∆V
OS
AV
CC
or DV
CC
= 5V ±5% - ±0.125 - LSB
Gain Error Sensitivity, ∆FSE AV
CC
or DV
CC
= 5V ±5% - ±0.15 - LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
Electrical Specifications AV
CC1,2
= DV
CC1,2
= +5.0V, DV
CC3
= +3.0V; V
RIN
= 2.50V; f
S
= 60MSPS at 50% Duty Cycle;
C
L
= 10pF; T
A
= 25
o
C; Differential Analog Input; Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
HI5662
3-8
Timing Waveforms
NOTES:
4. S
N
: N-th sampling period.
5. H
N
: N-th holding period.
6. B
M
,
N
: M-th stage digital output corresponding to N-th sampled input.
7. D
N
: Final data output corresponding to N-th sampled input.
FIGURE 1. HI5662 INTERNAL CIRCUIT TIMING
FIGURE 2. HI5662 INPUT-TO-OUTPUT TIMING
D
N - 6
D
N - 5
D
N - 1
D
N
D
N + 1
D
N + 2
ANALOG
INPUT
CLOCK
INPUT
INPUT
S/H
1ST
STAGE
2ND
STAGE
M-th
STAGE
DATA
OUTPUT
S
N - 1
H
N - 1
S
N
H
N
S
N + 1
H
N + 1
S
N + 2
S
N + 5
H
N + 5
S
N + 6
H
N + 6
S
N + 7
H
N + 7
S
N + 8
H
N + 8
B
1
,
N - 1
B
1
,
N
B
1
,
N + 1
B
1
,
N + 4
B
1
,
N + 5
B
1
,
N + 6
B
1
,
N + 7
B
2
,
N - 2
B
2
,
N - 1
B
2
,
N
B
2
,
N + 4
B
2
,
N + 5
B
2
,
N + 6
B
9
,
N - 5
B
9
,
N - 4
B
9
,
N
B
9
,
N + 1
B
9
,
N + 2
B
9
,
N + 3
t
LAT
t
OD
t
H
DATA N-1
DATA N
CLOCK
INPUT
DATA
OUTPUT
1.5V
t
AP
ANALOG
INPUT
t
AJ
1.5V
2.4V
0.5V
HI5662
3-9
Typical Performance Curves
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) AND
SINAD vs INPUT FREQUENCY
FIGURE 4. SNR vs INPUT FREQUENCY
FIGURE 5. -THD, -2HD AND -3HD vs INPUT FREQUENCY FIGURE 6. SINAD, SNR AND -THD vs INPUT AMPLITUDE
FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs
SAMPLE CLOCK DUTY CYCLE
FIGURE 8. SUPPLY CURRENT vs SAMPLE CLOCK
FREQUENCY
8
7
6
5
50
44
38
32
SINAD (dB)
ENOB (BITS)
1 10 100
INPUT FREQUENCY (MHz)
f
S
= 60MSPS
T
A
= 25
o
C
50
44
38
32
1 10 100
SNR (dB)
INPUT FREQUENCY (MHz)
f
S
= 60MSPS
T
A
= 25
o
C
90
60
55
50
1 10 100
INPUT FREQUENCY (MHz)
f
S
= 60MSPS
T
A
= 25
o
C
85
80
75
70
65
-3HD
-THD
-2HD
dBc
30
20
10
dB
INPUT LEVEL (dBFS)
70
60
50
40
-40 -10 0-30 -20
SNR (dB) OR SINAD (dB)
-THD (dBc)
DUTY CYCLE (%, t
HI
/t
CLK
)
42 44 46 48 50 52 5440
ENOB (BITS)
5
6
7
8
56 58 60
f
S
= 60MSPS
1MHz < f
IN
< 15MHz
T
A
= 25
o
C
f
S
(MSPS)
30 40 50 60 7020
SUPPLY CURRENT (mA)
0
10
30
40
50
60
70
20
10
100
110
120
130
140
90
80
150
1MHz < f
IN
< 15MHz
T
A
= 25
o
C
I
CC
AI
CC
DI
CC1
DI
CC2
DI
CC3
HI5662
P1-P3P4-P6P7-P9P10-P12P13-P14

HI5662/6IN

Mfr. #:
Buy HI5662/6IN
Manufacturer:
Renesas / Intersil
Description:
IC ADC 8BIT PIPELINED 44MQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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