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MAX1204AEAP+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
19
Maxim Integrated
Figure 17, the Reference-Adjust Circuit, shows how to
adjust ADC gain in applications that use the internal
reference. The circuit provides ±1.5% (±16 LSBs) of
gain-adjustment range.
Layout, Grounding, Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 18 shows the recommended system-ground con-
nections. Establish a single-point analog ground (star
ground point) at GND. Connect all other analog grounds
to this ground. No other digital system ground should be
connected to this single-point analog ground. The
ground return to the power supply should be low imped-
ance and as short as possible for noise-free operation.
High-frequency noise in the V
DD
power supply may affect
the high-speed comparator in the ADC. Bypass these
supplies to the single-point analog ground with 0.1µF and
4.7µF bypass capacitors close to the MAX1204. Minimize
capacitor lead lengths for best supply-noise rejection. If
the +5V power supply is very noisy, a 10Ω resistor can
be connected as a lowpass filter, as shown in Figure 18.
3.0
2.5
2.0
1.5
1.0
0.5
0
0.0001 0.001 0.01 0.1 1 10
TIME IN SHUTDOWN (sec)
POWER-UP DELAY (ms)
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
Figure 14a. MAX1204 Supply Current vs. Sample Rate/Second,
FULLPD, 400kHz Clock
1000
1
0 100 300 500
FULL POWER-DOWN
10
100
MAX186-14A
CONVERSIONS PER CHANNEL PER SECOND
200 400
2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION
50 150 250 350 450
8 CHANNELS
1 CHANNEL
AVERAGE SUPPLY CURRENT (µA)
Figure 14b. MAX1204 Supply Current vs. Sample Rate/Second,
FASTPD, 2MHz Clock
10,000
10
0
FAST POWER-DOWN
100
1000
CONVERSIONS PER CHANNEL PER SECOND
2k
8 CHANNELS
1 CHANNEL
4k 6k 8k 10k 12k 14k 16k 18k
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50
µ
s WAIT
AVERAGE SUPPLY CURRENT (µA)
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
20
Maxim Integrated
+5V
510kΩ
100kΩ
24kΩ
0.01µF
12
REFADJ
MAX1204
Figure 17. Reference-Adjust Circuit
+5V
-5V +3V
GND
SUPPLIES
DGND+3VV
L
V
SS
GNDV
DD
DIGITAL
CIRCUITRY
MAX1204
R* = 10Ω
*OPTIONAL
Figure 18. Power-Supply Grounding Connection
Figure 15. Unipolar Transfer Function, 4.096V = Full Scale
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
123
0
FS
FS - 3/2 LSB
FS = +4.096V
1 LSB =
FS
1024
INPUT VOLTAGE (LSBs)
Figure 16. Bipolar Transfer Function, ±4.096V/2 = Full Scale
011 . . . 111
OUTPUT CODE
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
-FS
0V
INPUT VOLTAGE (LSBs)
+FS - 1 LSB
FS =
+4.096V
2
1 LSB =
+4.096V
1024
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
21
Maxim Integrated
TMS320CL3x to MAX1204 Interface
Figure 19 shows an application circuit to interface the
MAX1204 to the TMS320 in external clock mode. Figure
20 is the timing diagram for this interface circuit.
Use the following steps to initiate a conversion in the
MAX1204 and to read the results.
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
The TMS320’s CLKX and CLKR are tied together with
the MAX1204’s SCLK input.
2) The MAX1204’s CS is driven low by the TMS320’s
XF_ I/O port to enable data to be clocked into the
MAX1204’s DIN.
3) Write an 8-bit word (1XXXXX11) to the MAX1204 to
initiate a conversion and place the device into exter-
nal clock mode. Refer to Table 2 to select the proper
XXXXX bit values for your specific application.
4) The MAX1204’s SSTRB output is monitored via the
TMS320’s FSR input. A falling edge on the SSTRB
output indicates that the conversion is in progress
and data is ready to be received from the MAX1204.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits repre-
sent the 10-bit conversion result followed by two
sub-bits and four trailing bits, which should be
ignored.
6) Pull CS high to disable the MAX1204 until the next
conversion is initiated.
Figure 19. MAX1204 to TMS320 Serial Interface
XF
CLKX
CLKR
DX
DR
FSR
CS
SCLK
DIN
DOUT
SSTRB
TMS320LC3x
MAX1204
Figure 20. TMS320 Serial-Interface Timing Diagram
CS
SCLK
DIN
SSTRB
DOUT
START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0
MSB LSB
HIGH
IMPEDANCE
HIGH
IMPEDANCE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

MAX1204AEAP+T

Mfr. #:
Buy MAX1204AEAP+T
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 8Ch 133ksps 5V Precision ADC
Lifecycle:
New from this manufacturer.
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