MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
4
Maxim Integrated
Internal compensation mode
Fast power-down (Note 9)
External compensation mode
CONDITIONS
µF
0
Capacitive Bypass at REF
µA
30 70
I
DD
Positive Supply Current
V0 or -5 ±5%V
SS
Negative Supply Voltage
V5 ±5%V
DD
Positive Supply Voltage
4.7
V/V1.68Reference-Buffer Gain
µA±50REFADJ Input Current
UNITSMIN TYP MAXSYMBOLPARAMETER
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= +5V ±5%, V
L
= 2.7V to 3.6V; V
SS
= 0V or -5V ±5%; f
SCLK
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
Operating mode mA1.5 2.5
Operating mode and fast power-down
µA
50
I
SS
Negative Supply Current
Full power-down (Note 9) 210
Full power-down 10
V2.70 5.25V
L
Logic Supply Voltage
V
L
= V
DD
= 5V µA10I
VL
Logic Supply Current (Notes 6, 10)
V
DD
= 5V ±5%; external reference, 4.096V;
full-scale input
mV±0.06 ±0.5PSR
Positive Supply Rejection
(Note 11)
V
SS
= -5V ±5%; external reference, 4.096V;
full-scale input
mV±0.01 ±0.5PSR
Negative Supply Rejection
(Note 11)
External reference, 4.096V; full-scale input mV±0.06 ±0.5PSR
Logic Supply Rejection
(Note 12)
µA
EXTERNAL REFERENCE AT REFADJ
POWER REQUIREMENTS
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
5
Maxim Integrated
CS = V
L
(Note 6)
CS = V
L
I
SOURCE
= 1mA
I
SINK
= 3mA
SHDN = open
V
SHDN
= 0V
SHDN = V
DD
(Note 6)
V
IN
= 0V or V
DD
CONDITIONS
pF15C
OUT
Three-State Output Capacitance
µA±10I
L
Three-State Leakage Current
VV
L
- 0.5V
OH
Output Voltage High
V
0.4
V
OL
Output Voltage Low
nA-100 100
SHDN Maximum Allowed
Leakage, Mid-Input
µA-4.0I
SL
SHDN Input Current, Low
µA4.0I
SH
SHDN Input Current, High
VV
DD
- 0.5V
SH
SHDN Input High Voltage
V0.8V
IL
V2.0V
IH
DIN, SCLK, CS Input High Voltage
DIN, SCLK, CS Input Low Voltage
pF15C
IN
DIN, SCLK, CS Input Capacitance
µA±1I
IN
DIN, SCLK, CS Input Leakage
V0.15V
HYST
DIN, SCLK, CS Input Hysteresis
UNITSMIN TYP MAXSYMBOLPARAMETER
ELECTRICAL CHARACTERISTICS
(V
DD
= +5V ±5%, V
L
= 2.7V to 5.25V; V
SS
= 0V or -5V ±5%; f
SCLK
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
I
SINK
= 5mA
V
0.4
V
OL
Output Voltage Low
I
SINK
= 8mA 0.3
I
SINK
= 6mA 0.3
I
SOURCE
= 1mA V4V
OH
Output Voltage High
V
CS
= 5V µA±10I
L
Three-State Leakage Current
V
CS
= 5V (Note 6) pF15C
OUT
Three-State Output Capacitance
V1.5 V
DD
- 1.5V
SM
SHDN Input Mid-Voltage
V0.5V
SL
SHDN Input Low Voltage
SHDN = open
V2.75V
FLT
SHDN Voltage, Open
DIGITAL INPUTS: DIN, SCLK, CS, SHDN
DIGITAL OUTPUTS: DOUT, SSTRB (V
L
= 2.7V to 3.6V)
DIGITAL OUTPUTS: DOUT, SSTRB (V
L
= 4.75V to 5.25V)
C
LOAD
= 100pF
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
6
Maxim Integrated
External clock mode only, C
LOAD
= 100pF ns240
C
LOAD
= 100pF ns
ns20 240t
DO
SCLK Fall to Output Data Valid
CONDITIONS
240t
DV
CS Fall to Output Enable
C
LOAD
= 100pF ns240t
TR
CS Rise to Output Disable
t
SDV
CS Fall to SSTRB Output Enable
(Note 6)
External clock mode only, C
LOAD
= 100pF ns240t
STR
CS Rise to SSTRB Output
Disable (Note 6)
Internal clock mode only ns0t
SCK
SSTRB Rise to SCLK Rise
(Note 6)
ns0t
DH
DIN to SCLK Hold
µs1.5t
ACQ
Acquisition Time
ns100t
DS
DIN to SCLK Setup
UNITSMIN TYP MAXSYMBOLPARAMETER
TIMING CHARACTERISTICS
(V
DD
= +5V ±5%, V
L
= 2.7V to 3.6V, V
SS
= 0V or -5V ±5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
ns100t
CSS
CS to SCLK Rise Setup
ns0t
CSH
CS to SCLK Rise Hold
ns200t
CH
SCLK Pulse Width High
ns200t
CL
SCLK Pulse Width Low
C
LOAD
= 100pF ns240t
SSTRB
SCLK Fall to SSTRB
C
LOAD
= 100pF
Note 1: Tested at V
DD
= 5.0V; V
SS
= 0V; unipolar input mode.
Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is
calibrated.
Note 3: Internal reference, offset nulled.
Note 4: On-channel grounded; sine-wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for analog inputs is from V
SS
to V
DD
.
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with V
L
at 3.3V, and with all digital inputs tied to either V
L
or GND (Figure 12c);
REFADJ = GND.
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
active (CS low), the logic supply current depends on f
SCLK
, and on the static and capacitive load at DOUT and SSTRB.
Note 11: Measured at V
SUPPLY
+5% and V
SUPPLY
-5% only.
Note 12: Measured at V
L
= 2.7V and V
L
= 3.6V.

MAX1204AEAP+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 8Ch 133ksps 5V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
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