PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 25 September 2014 16 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
9. Bus transactions
Data is transmitted to the PCA9574 registers using ‘Write Byte’ transfers (see Figure 11
and Figure 12
).
Data is read from the PCA9574 registers using ‘Read Byte’ transfers (see Figure 13
and
Figure 14
).
Fig 11. Write to Output port register
0 AS
slave address
START condition R/W acknowledge
from slave
002aad057
00001010
command byte
A
acknowledge
from slave
12345678SCL 9
SDA
DATA 1 A
write to port
data out from port
t
v(Q)
acknowledge
from slave
DATA 1 VALID
data to port
10000A00
P
STOP
condition
Fig 12. Write to Polarity inversion, Bus-hold enable, Pull-up/pull-down selector, Configuration, Interrupt mask
and Interrupt status registers
0 AS
slave address
START condition R/W acknowledge
from slave
002aad058
0000XXX0
command byte
A
acknowledge
from slave
12345678SCL 9
SDA
DATA A
data to register
acknowledge
from slave
data to register
10000A00
P
STOP
condition
PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 25 September 2014 17 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
Fig 13. Read from register
10000A00AS0
START condition R/W
acknowledge
from slave
002aad059
A
acknowledge
from slave
SDA
A P
command byte
acknowledge
from master
data from register
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
10000A01A0
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
data from register
DATA (last byte)
This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition.
Fig 14. Read Input port register
10000A01AS0
slave address
START condition R/W acknowledge
from slave
002aad060
data from port
A
acknowledge
from master
SDA 1
no acknowledge
from master
read from
port
data into
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2
DATA 3
P
STOP
condition
t
v(INT)
t
rst(INT)
t
h(D)
t
su(D)
2345678
SCL
91
PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 25 September 2014 18 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
10. Application design-in information
11. Limiting values
Device address configured as 0100 0000b for this example.
P0, P2, P3 configured as outputs.
P1, P4, P5 configured as inputs.
P6, P7 are not used and must be configured as outputs.
Fig 15. Typical application
PCA9574
P0
P1
SCL
SDA
V
DD
SCL
SDA
P2
P3
V
DD
V
SS
MASTER
CONTROLLER
V
SS
V
DD
= 1.1 V to 3.6 V
SUBSYSTEM 1
(e.g., temp. sensor)
INT
SUBSYSTEM 2
(e.g., counter)
RESET
controlled switch
(e.g., CBT device)
A
B
enable
INT
V
DD(IO)
INT
1.1 kΩ 2 kΩ
SUBSYSTEM 3
(e.g., alarm system)
ALARM
P4
P5
V
DD(IO)
A0
P6
P7
1.6 kΩ1.6 kΩ
RESETRESET
V
DD(IO)
= 3.6 V
002aad061
SUBSYSTEM 4
(e.g., RF module)
CTRL
Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +4.0 V
V
DD(IO)
input/output supply voltage V
SS
0.5 V
DD
+0.5 V
I
I/O
input/output current - 5mA
I
I
input current - 20 mA
I
DD
supply current - 90 mA
I
SS
ground supply current - 90 mA
P
tot
total power dissipation - 75 mW
T
stg
storage temperature 65 +150 C
T
amb
ambient temperature 40 +85 C

PCA9574HR,115

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC I/O EXPANDER I2C 8B 16HXQFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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