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MC100EP195BMNG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
MC100EP195B
http://onsemi.com
13
Table 11. Delay Value of Two EP195B Cascaded
VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2
INPUT FOR CHIP #1 Total
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Delay Value Delay Value
0 0 0 0 0 0 0 0 0 0 0 0 ps 4400 ps
0 0 0 0 0 0 0 0 0 0 1 10 ps 4410 ps
0 0 0 0 0 0 0 0 0 1 0 20 ps 4420 ps
0 0 0 0 0 0 0 0 0 1 1 30 ps 4430 ps
0 0 0 0 0 0 0 0 1 0 0 40 ps 4440 ps
0 0 0 0 0 0 0 0 1 0 1 50 ps 4450 ps
0 0 0 0 0 0 0 0 1 1 0 60 ps 4460 ps
0 0 0 0 0 0 0 0 1 1 1 70 ps 4470 ps
0 0 0 0 0 0 0 1 0 0 0 80 ps 4480 ps
0 0 0 0 0 0 1 0 0 0 0 160 ps 4560 ps
0 0 0 0 0 1 0 0 0 0 0 220 ps 4720 ps
0 0 0 0 1 0 0 0 0 0 0 640 ps 5040 ps
0 0 0 1 0 0 0 0 0 0 0 1280 ps 5680 ps
0 0 1 0 0 0 0 0 0 0 0 2560 ps 6960 ps
0 1 0 0 0 0 0 0 0 0 0 5120 ps 9520 ps
0 1 1 1 1 1 1 1 1 1 1 10230 ps 14630 ps
VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2
INPUT FOR CHIP #1 Total
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Delay Value Delay Value
1 0 0 0 0 0 0 0 0 0 0 10240 ps 14640 ps
1 0 0 0 0 0 0 0 0 0 1 10250 ps 14650 ps
1 0 0 0 0 0 0 0 0 1 0 10260 ps 14660 ps
1 0 0 0 0 0 0 0 0 1 1 10270 ps 14670 ps
1 0 0 0 0 0 0 0 1 0 0 10280 ps 14680 ps
1 0 0 0 0 0 0 0 1 0 1 10290 ps 14690 ps
1 0 0 0 0 0 0 0 1 1 0 10300 ps 14700 ps
1 0 0 0 0 0 0 0 1 1 1 10310 ps 14710 ps
1 0 0 0 0 0 0 1 0 0 0 10320 ps 14720 ps
1 0 0 0 0 0 1 0 0 0 0 10400 ps 14800 ps
1 0 0 0 0 1 0 0 0 0 0 10560 ps 14960 ps
1 0 0 0 1 0 0 0 0 0 0 10880 ps 15280 ps
1 0 0 1 0 0 0 0 0 0 0 11520 ps 15920 ps
1 0 1 0 0 0 0 0 0 0 0 12800 ps 17200 ps
1 1 0 0 0 0 0 0 0 0 0 15360 ps 19760 ps
1 1 1 1 1 1 1 1 1 1 1 20470 ps 24870 ps
MC100EP195B
http://onsemi.com
14
Multi−Channel Deskewing
The most practical application for EP195B is in multiple
channel delay matching. Slight differences in impedance and
cable length can create large timing skews within a high−speed
system. To deskew multiple signal channels, each channel can
be sent through each EP195B as shown in Figure 7. One signal
channel can be used as reference and the other EP195Bs can
be used to adjust the delay to eliminate the timing skews.
Nearly any high−speed system can be fine−tuned (as small as
10 ps) to reduce the skew to extremely tight tolerances.
EP195B
IN Q
IN
Q
#1
EP195B
IN Q
IN
Q
#2
EP195B
IN Q
IN
Q
#N
Digital
Data
Control
Logic
Figure 7. Multiple Channel Deskewing Diagram
Measure Unknown High Speed Device Delays
EP195Bs provide a possible solution to measure the
unknown delay of a device with a high degree of precision.
By combining two EP195Bs and EP31 as shown in Figure
8, the delay can be measured. The first EP195B can be set
to SETMIN and its output is used to drive the unknown delay
device, which in turn drives the input of a D flip−flop of
EP31. The second EP195B is triggered along with the first
EP195B and its output provides a clock signal for EP31.
The programmed delay of the second EP195B is varied to
detect the output edge from the unknown delay device.
If the programmed delay through the second EP195B is too
long, the flip−flop output will be at logic high. On the other
hand, if the programmed delay through the second EP195B is
too short, the flip−flop output will be at a logic low. If the
programmed delay is correctly fine−tuned in the second
EP195B, the flip−flop will bounce between logic high and
logic low. The digital code in the second EP195B can be
directly correlated into an accurate device delay.
EP195B
IN Q
IN
Q
#1
EP195B
IN Q
IN
Q
#2
Unknown Delay
Device
Control
Logic
D
CLK
Q
Q
EP31
CLOCK
CLOCK
Figure 8. Multiple Channel Deskewing Diagram
MC100EP195B
http://onsemi.com
15
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50 W
Z
o
= 50 W
50 W 50 W
V
TT
V
TT
= V
CC
− 2.0 V
ORDERING INFORMATION
Device Package Shipping
†
MC100EP195BFAG LQFP−32
(Pb−Free)
250 Units / tray
MC100EP195BFAR2G LQFP−32
(Pb−Free)
2000 / Tape & Reel
MC100EP195BMNG QFN−32
(Pb−Free)
74 Units / Rail
MC100EP195BMNR4G QFN−32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D −
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1642/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
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MC100EP195BMNG

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Buy MC100EP195BMNG
Manufacturer:
ON Semiconductor
Description:
Delay Lines / Timing Elements PROGR DELAY CHIP
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