10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/14/08
IS62WV6416ALL, IS62WV6416BLL
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(CS1 Controlled, OE = HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
CS2
WE
DOUT
DIN
LB, UB
t
PWB
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
45ns 55 ns
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 45 — 55 — ns
tSCS1/tSCS2 CS1/CS2 to Write End 35 — 45 — ns
tAW Address Setup Time to Write End 35 — 45 — ns
tHA Address Hold from Write End 0 — 0 — ns
tSA Address Setup Time 0 — 0 — ns
tPWB LB, UB Valid to End of Write 35 — 45 — ns
tPWE WE Pulse Width 35 — 40 — ns
tSD Data Setup to Write End 20 — 25 — ns
tHD Data Hold from Write End 0 — 0 — ns
tHZWE
(3)
WE LOW to High-Z Output — 20 — 20 ns
tLZWE
(3)
WE HIGH to Low-Z Output 5 — 5 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
VDD-0.2V/VDD-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
