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AD8803ARZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Octal 8-Bit TrimDAC
with Power Shutdown
AD8801/AD8803
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
FEATURES
Low Cost
Replaces Eight Potentiometers
Eight Individually Programmable Outputs
Three-Wire Serial Input
Power Shutdown ≤ 25 mW Including I
DD
and I
REF
Midscale Preset, AD8801
Separate V
REFL
Range Setting, AD8803
+3 V to +5 V Single Supply Operation
APPLICATIONS
Automatic Adjustment
Trimmer Potentiometer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment
GENERAL DESCRIPTION
The AD8801/AD8803 provides eight digitally controlled dc
voltage outputs. This potentiometer divider TrimDAC
®
allows
replacement of the mechanical trimmer function in new designs.
The AD8801/AD8803 is ideal for dc voltage adjustment
applications.
Easily programmed by serial interfaced microcontroller ports,
the AD8801 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli-
cations such as gain control of video amplifiers, voltage con-
trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com-
puter graphic displays are a few of the many applications ideally
suited for these parts. The AD8803 provides independent con-
trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
V
REFL
pin. This is helpful for maximizing the resolution of de-
vices with a limited allowable voltage control range.
FUNCTIONAL BLOCK DIAGRAM
(DACs 2–7 Omitted for Clarity)
Internally the AD8801/AD8803 contain eight voltage output
digital-to-analog converters, sharing a common reference volt-
age input.
Each DAC has its own DAC register that holds its output state.
These DAC registers are updated from an internal serial-to-par-
allel shift register that is loaded from a standard three-wire serial
input digital interface. Eleven data bits make up the data word
clocked into the serial input register. This data word is decoded
where the first 3 bits determine the address of the DAC register
to be loaded with the last 8 bits of data. The AD8801/AD8803
consumes only 5 µA from 5 V power supplies. In addition, in
shutdown mode reference input current consumption is also re-
duced to 5 µA while saving the DAC latch settings for use after
return to normal operation.
The AD8801/AD8803 is available in 16-pin plastic DIP and the
1.5 mm height SO-16 surface mount packages.
TrimDAC is a registered trademark of Analog Devices, Inc.
DAC 8
V
OUT
V
REFH
V
REFL
.
.
.
.
.
.
AD8801/AD8803
V
REFL
V
REFH
O1
O8
SHDNRS
CS
CLK
SDI
GND
V
DD
8
8
8
88
8
3
DAC
SELECT
11-BIT
SERIAL
LATCH
D
CK
RS
1
8
ADDRESS
8-BIT
LATCH
CK
RS
8-BIT
LATCH
CK RS
DAC 1
V
OUT
V
REFH
V
REFL
See the AD8802/AD8804 for a twelve channel version of this product.
REV. A
–2–
Parameter Symbol Conditions Min Typ
1
Max Units
STATIC ACCURACY
Specifications Apply to All DACs
Resolution N 8 Bits
Integral Nonlinearity Error INL –1.5 ±1/2 +1.5 LSB
Differential Nonlinearity DNL Guaranteed Monotonic –1 ±1/4 +1 LSB
Full-Scale Error G
FSE
–4 –2.8 +0.5 LSB
Zero-Code Error V
ZSE
–0.5 ±0.1 +0.5 LSB
DAC Output Resistance R
OUT
358 kΩ
Output Resistance Match ∆R/R
O
1%
REFERENCE INPUT
Voltage Range
2
V
REFH
0V
DD
V
V
REFL
Pin Available on AD8803 Only 0 V
DD
V
Input Resistance R
REFH
Digital Inputs = 55
H
, V
REFH
= V
DD
2kΩ
Reference Input Capacitance
3
C
REF0
Digital Inputs All Zeros 25 pF
C
REF1
Digital Inputs All Ones 25 pF
DIGITAL INPUTS
Logic High V
IH
V
DD
= +5 V 2.4 V
Logic Low V
IL
V
DD
= +5 V 0.8 V
Logic High V
IH
V
DD
= +3 V 2.1 V
Logic Low V
IL
V
DD
= +3 V 0.6 V
Input Current I
IL
V
IN
= 0 V or +5 V ±1 µA
Input Capacitance
3
C
IL
5pF
POWER SUPPLIES
4
Power Supply Range V
DD
Range 2.7 5.5 V
Supply Current (CMOS) I
DD
V
IH
= V
DD
or V
IL
= 0 V 0.01 5 µA
Supply Current (TTL) I
DD
V
IH
= 2.4 V or V
IL
= 0.8 V, V
DD
= +5.5 V 1 4 mA
Shutdown Current I
REFH
SHDN = 0 0.01 5 µA
Power Dissipation P
DISS
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= +5.5 V 27.5 µW
Power Supply Sensitivity PSRR V
DD
= 5 V ± 10%, V
REFH
= +4.5 V 0.001 0.002 %/%
Power Supply Sensitivity PSRR V
DD
= 3 V ± 10%, V
REFH
= +2.7 V 0.01 %/%
DYNAMIC PERFORMANCE
3
V
OUT
Settling Time (Positive or Negative) t
S
±1/2 LSB Error Band 0.6 µs
Crosstalk CT See Note 5, f = 100 kHz 50 dB
SWITCHING CHARACTERISTICS
3, 6
Input Clock Pulse Width t
CH
, t
CL
Clock Level High or Low 15 ns
Data Setup Time t
DS
5ns
Data Hold Time t
DH
5ns
CS Setup Time t
CSS
10 ns
CS High Pulse Width t
CSW
10 ns
Reset Pulse Width t
RS
60 ns
CLK Rise to
CS Rise Hold Time t
CSH
15 ns
CS Rise to Next Rising Clock t
CS1
10
ns
NOTES
1
Typical values represent average readings measured at +25°C.
2
V
REFH
can be any value between GND and V
DD
, for the AD8803 V
REFL
can be any value between GND and V
DD
.
3
Guaranteed by design and not subject to production test.
4
Digital Input voltages V
IN
= 0 V or V
DD
for CMOS condition. DAC outputs unloaded. P
DISS
is calculated from (I
DD
× V
DD
).
5
Measured at a V
OUT
pin where an adjacent V
OUT
pin is making a full-scale voltage change.
6
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of V
DD
) and timed from a voltage
level of 1.6 V.
Specifications subject to change without notice.
AD8801/AD8803–SPECIFICATIONS
(V
DD
= +3 V 6 10% or +5 V 6 10%, V
REFH
= +V
DD
, V
REFL
= 0 V, –408C
≤ T
A
≤ +858C unless otherwise noted)
AD8801/AD8803
REV. A
–3–
ORDERING GUIDE
Package Package
Model FTN Temperature Description Option
AD8801AN
RS –40°C to +85°C PDIP-16 N-16
AD8801AR
RS –40°C to +85°C SO-16 R-16A
AD8803AN REFL –40°C to +85°C PDIP-16 N-16
AD8803AR REFL –40°C to +85°C SO-16 R-16A
AD8803 PIN DESCRIPTIONS
Pin Name Description
1V
REFH
Common High-Side DAC Reference Input
2 O1 DAC Output #1, Addr = 000
2
3 O2 DAC Output #2, Addr = 001
2
4 O3 DAC Output #3, Addr = 010
2
5 O4 DAC Output #4, Addr = 011
2
6 SHDN Reference inputs open circuit, active low, all
DAC outputs open circuit. DAC latch settings
maintained.
7
CS Chip Select Input, active low. When CS returns
high, data in the serial input register is decoded
based on the address bits and loaded into the tar-
get DAC register.
8 GND Ground
9V
REFL
Common Low-Side DAC Reference Input
10 CLK Serial Clock Input, Positive Edge Triggered
11 SDI Serial Data Input
12 O5 DAC Output #5, Addr = 100
2
13 O6 DAC Output #6, Addr = 101
2
14 O7 DAC Output #7, Addr = 110
2
15 O8 DAC Output #8, Addr = 111
2
16 V
DD
Positive power supply, specified for operation at
both +3 V and +5 V.
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C, unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +8 V
V
REFX
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . 0 V, V
DD
Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C
Maximum Junction Temperature (T
J
MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . .(T
J
MAX – T
A
)/θ
JA
Thermal Resistance θ
JA,
SOIC (SO-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
P-DIP (N-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
AD8801 PIN DESCRIPTIONS
Pin Name Description
1V
REFH
Common DAC Reference Input
2 O1 DAC Output #1, Addr = 000
2
3 O2 DAC Output #2, Addr = 001
2
4 O3 DAC Output #3, Addr = 010
2
5 O4 DAC Output #4, Addr = 011
2
6 SHDN Reference input open circuit, active low, all
DAC outputs open circuit. DAC latch settings
maintained.
7
CS Chip Select Input, active low. When CS returns
high, data in the serial input register is decoded
based on the address bits and loaded into the tar-
get DAC register.
8 GND Ground
9 CLK Serial Clock Input, Positive Edge Triggered
10 SDI Serial Data Input
11 O5 DAC Output #5, Addr = 100
2
12 O6 DAC Output #6, Addr = 101
2
13 O7 DAC Output #7, Addr = 110
2
14 O8 DAC Output #8, Addr = 111
2
15 RS Asynchronous preset to midscale output setting,
active low. Loads all DAC latches with 80
H
.
16 V
DD
Positive power supply, specified for operation at
both +3 V and +5 V.
PIN CONFIGURATIONS
V
REFH
O1
V
DD
RS
O4
SHDN
CS
O6
O5
SDI
O2
O3
O8
O7
GND CLK
1
2
16
15
5
6
7
12
11
10
3
4
14
13
89
TOP VIEW
(Not to Scale)
AD8801
V
REFH
O1
V
DD
O8
O4
SHDN
CS
O5
SDI
CLK
O2
O3
O7
O6
GND V
REFL
1
2
16
15
5
6
7
12
11
10
3
4
14
13
89
TOP VIEW
(Not to Scale)
AD8803
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

AD8803ARZ

Mfr. #:
Buy AD8803ARZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Octal 8-Bit w/ Power Shutdown
Lifecycle:
New from this manufacturer.
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