1. General description
The 74LV32 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC32 and 74HCT32.
The 74LV32 provides a quad 2-input OR function.
2. Features
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25 °C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
=25°C
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 °Cto+85°C and from 40 °C to +125 °C
3. Ordering information
74LV32
Quad 2-input OR gate
Rev. 03 — 9 November 2007 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LV32N 40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74LV32D 40 °C to +125 °C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LV32DB 40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LV32PW 40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LV32BQ 40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
SOT762-1
74LV32_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 9 November 2007 2 of 15
NXP Semiconductors
74LV32
Quad 2-input OR gate
4. Functional diagram
5. Pinning information
5.1 Pinning
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
mna242
1A
1B
1Y
2
1
3
2A
2B
2Y
5
4
6
3A
3B
3Y
10
9
8
4A
4B
4Y
13
12
11
mna243
3
1
1
1
1
2
1
6
5
4
8
10
9
11
13
12
mna241
A
B
Y
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14
74LV32
1A V
CC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y
001aah104
1
2
3
4
5
6
7
8
10
9
12
11
14
13
001aah105
74LV32
Transparent top view
V
CC
(1)
2Y 3A
2B 3B
2A 4Y
1Y 4A
1B 4B
GND
3Y
1A
V
CC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
74LV32_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 9 November 2007 3 of 15
NXP Semiconductors
74LV32
Quad 2-input OR gate
5.2 Pin description
6. Functional description
7. Limiting values
Table 2. Pin description
Symbol Pin Description
1A 1 data input
1B 2 data input
1Y 3 data output
2A 4 data input
2B 5 data input
2Y 6 data output
GND 7 ground (0 V)
3Y 8 data output
3A 9 data input
3B 10 data input
4Y 11 data output
4A 12 data input
4B 13 data input
V
CC
14 supply voltage
Table 3. Function selection
H = HIGH voltage level; L = LOW voltage level; X = don’t care
Input Output
nA nB nY
HXH
XHH
LLL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7.0 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+ 0.5 V
[1]
- ±20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+ 0.5 V
[1]
- ±50 mA
I
O
output current V
O
= 0.5 V to (V
CC
+ 0.5 V) - ±25 mA
I
CC
supply current - 50 mA
I
GND
ground current 50 - mA
T
stg
storage temperature 65 +150 °C

74LV32D,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Logic Gates QUAD 2-INPUT OR GATE
Lifecycle:
New from this manufacturer.
Delivery:
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