74LV32_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 9 November 2007 7 of 15
NXP Semiconductors
74LV32
Quad 2-input OR gate
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. The input (nA, nB) to output (nY) propagation delays
mna244
t
PHL
t
PLH
V
M
V
M
nA, nB input
nY output
GND
V
I
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
M
V
M
< 2.7 V 0.5V
CC
0.5V
CC
2.7 V to 3.6 V 1.5 V 1.5 V
≥ 4.5 V 0.5V
CC
0.5V
CC
Test data is given in Table 9.
Definitions test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
Fig 7. Load circuit for switching times
V
CC
V
I
V
O
001aaa663
D.U.T.
C
L
50 pF
R
T
R
L
1 kΩ
PULSE
GENERATOR
Table 9. Test data
Supply voltage
V
CC
Input
V
I
t
r
, t
f
< 2.7 V V
CC
≤ 2.5 ns
2.7 V to 3.6 V 2.7 V ≤ 2.5 ns
≥ 4.5 V V
CC
≤ 2.5 ns