DS2740BU+ Datasheet DS2740U+, DS2740BU+ | P7-P9

DS2740

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ACR RANGE

SNS

PART

IS1

- V

IS2

20mΩ 15mΩ 10mΩ 5mΩ

DS2740U

DS2740BU

±204.8mVh ±10.24Ah ±13.65Ah ±20.48Ah ±40.96Ah

MEMORY

The DS2740 has memory space with registers for instrumentation, status, and control. When the MSB of

a two-byte register is read, both the MSB and LSB are latched and held for the duration of the Read Data

command to prevent updates during the read and ensure synchronization between the two register bytes.

For consistent results, always read the MSB and the LSB of a two-byte register during the same Read

Data command sequence.

Table 3. MEMORY MAP

ADDRESS (HEX) DESCRIPTION READ/WRITE

00 Reserved —

01 Status Register R/W

02 to 07 Reserved —

08 Special Feature Register R/W

09 to 0D Reserved —

0E Current Register MSB R

0F Current Register LSB R

10 Accumulated Current Register MSB R/W

11 Accumulated Current Register LSB R/W

12 to FF Reserved —

STATUS REGISTER

The format of the status register is shown in Figure 5. The function of each bit is described in detail in the

following paragraphs.

Figure 5. STATUS REGISTER FORMAT

ADDRESS 01h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

X SMOD X RNAOP X X X X

SMOD

—SLEEP Mode Enable. A value of 1 allows the DS2740 to enter Sleep mode when DQ is low for

2s. A value of 0 disables DQ related transitions to Sleep mode. The power-up default of SMOD = 0.

RNAOP—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the Read Net Address

command to 33h, while a 1 sets the opcode to 39h. The power-up default of RNAOP = 0.

X—Reserved bits.

DS2740

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SPECIAL FEATURE REGISTER

The format of the special feature register is shown in Figure 6. The function of each bit is described in

detail in the following paragraphs.

Figure 6. SPECIAL FEATURE REGISTER FORMAT

ADDRESS 08

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

PIO X X X X X X

PIO—PIO Pin Sense and Control. This bit is read and write enabled. Writing a 0 to the PIO bit enables

the PIO open-drain output driver, forcing the PIO pin low. Writing a 1 to the PIO bit disables the output

driver, allowing the PIO pin to be pulled high or used as an input. Reading the PIO bit returns the logic

level forced on the PIO pin. Note that if PIO is left floating, the weak pulldown brings the pin low. PIO

resets to a 1 at initial power up, when the DS2740 enters Sleep mode, or DQ low > t

SLEEP

(independent of

the SMOD pin).

X—Reserved Bits.

1-Wire BUS SYSTEM

The 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a

1-Wire bus with multiple slaves. A single-drop bus has only one slave device. In all instances, the

DS2740 is a slave device. The bus master is typically a microprocessor in the host system. The discussion

of this bus system consists of four topics: 64-bit net address, hardware configuration, transaction

sequence, and 1-Wire signaling.

64-BIT NET ADDRESS

Each DS2740 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first

eight bits are the 1-Wire family code (36h for DS2740). The next 48 bits are a unique serial number. The

last eight bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 7). The 64-bit net

address and the 1-Wire I/O circuitry built into the device enable the DS2740 to communicate through the

1-Wire protocol detailed in the

1-Wire Bus System section of this data sheet.

Figure 7. 1-Wire NET ADDRESS FORMAT

8-BIT CRC 48-BIT SERIAL NUMBER

8-BIT FAMILY

CODE (36h)

MSb LSb

CRC GENERATION

The DS2740 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure

error-free transmission of the address, the host system can compute a CRC value from the first 56 bits of

the address and compare it to the CRC from the DS2740. The host system is responsible for verifying the

CRC value and taking action as a result. The DS2740 does not compare CRC values and does not prevent

a command sequence from proceeding as a result of a CRC mismatch. Proper use of the CRC can result

in a communication channel with a very high level of integrity.

DS2740

The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as

shown in Figure 8, or it can be generated in software. Additional information about the Dallas 1-Wire

CRC is available in Application Note 27,

Understanding and Using Cyclic Redundancy Checks with

Dallas Semiconductor iButton Products. (This application note can be found on the Maxim/Dallas

Semiconductor website at www.maxim-ic.com.)

In the circuit in Figure 8, the shift register bits are initialized to 0. Then, starting with the least significant

bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered,

then the serial number is entered. After the 48th bit of the serial number has been entered, the shift

Figure 8. 1-Wire CRC GENERATION BLOCK DIAGRAM

MSb

XOR

LSb

XOR

INPUT

HARDWARE CONFIGURATION

Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive

it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the

bus with open-drain or tri-state output drivers. The DS2740 uses an open-drain output driver as part of the

bidirectional interface circuitry shown in Figure 9. If a bidirectional pin is not available on the bus master,

separate output and input pins can be connected together.

The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the

value of this resistor should be approximately 5k

Ω. The idle state for the 1-Wire bus is high. If, for any

reason, a bus transaction must be suspended, the bus must be left in the idle state to properly resume the

transaction later. If the bus is left low for more than 120

μs (16μs for overdrive speed), slave devices on

the bus begin to interpret the low period as a reset pulse, effectively terminating the transaction.

The DS2740 can operate in two communication speed modes, standard and overdrive. The speed mode is

determined by the input logic level of the OVD pin with a logic 0 selecting standard Speed and a logic 1

selecting overdrive speed. The OVD pin must be at a stable logic level of 0 or 1 before initializing a

transaction with a reset pulse. All 1-Wire devices on a multinode bus must operate at the same

communication speed for proper operation. 1-Wire timing for both standard and overdrive speeds are

listed in the

Electrical Characteristics: 1-Wire Interface tables.

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