1. General description
The 74HC126; 74HCT126 is a quad buffer/line driver with 3-state outputs controlled by
the output enable inputs (nOE). A LOW on nOE causes the outputs to assume
a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Inverting outputs
Complies with JEDEC standard no. 7A
Input levels:
For 74HC126: CMOS level
For 74HCT126: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
74HC126; 74HCT126
Quad buffer/line driver; 3-state
Rev. 3 — 22 September 2014 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC126N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT126N
74HC126D 40 C to +125 C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74HCT126D
74HC126DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74HCT126DB
74HC126PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HCT126PW
74HC_HCT126 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 22 September 2014 2 of 16
NXP Semiconductors
74HC126; 74HCT126
Quad buffer/line driver; 3-state
4. Functional diagram
5. Pinning information
5.1 Pinning
Fig 1. Logic symbol Fig 2. IEC logic symbol
PQD
$ <
2(
$ <
2(
$ <

2(
$ <



2(
PQD
(1




Fig 3. Logic diagram (one buffer/line driver)
PQD
Q2(
Q$
Q<
Fig 4. Pin configuration for SOT27-1 and SOT108-1 Fig 5. Pin configuration for SOT337-1 and SOT402-1
+&
+&7
2( 9
&&
$
2(
<
$
2( <
$
2(
<
$
*1' <
DDD





+&
+&7
2( 9
&&
$
2(
<
$
2( <
$
2(
<
$
*1' <
DDD





74HC_HCT126 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 22 September 2014 3 of 16
NXP Semiconductors
74HC126; 74HCT126
Quad buffer/line driver; 3-state
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: P
tot
derates linearly with 12 mW/K above 70 C.
[3] For SO14 package: P
tot
derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60 C.
Table 2. Pin description
Symbol Pin Description
1OE, 2OE, 3OE, 4OE 1, 4, 10, 13 data enable input (active HIGH)
1A, 2A, 3A, 4A 2, 5, 9, 12 data input
1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
V
CC
14 supply voltage
Table 3. Function table
[1]
Control Input Output
nOE nA nY
HLL
HHH
LXZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+0.5 V
[1]
- 20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+0.5V
[1]
- 20 mA
I
O
output current 0.5 V < V
O
< V
CC
+0.5V - 35 mA
I
CC
supply current - 70 mA
I
GND
ground current 70 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
DIP14 package
[2]
- 750 mW
SO14 and (T)SSOP14 packages
[3]
- 500 mW

74HC126PW,118

Mfr. #:
Manufacturer:
Nexperia
Description:
Buffers & Line Drivers QUAD 3-STATE BUS BUF
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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