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BUK96150-55A,118

P1-P3P4-P6P7-P9
Philips Semiconductors Product specification
TrenchMOS transistor BUK95150-55A
Logic level FET BUK96150-55A
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in a
plastic envelope available in V
DS
Drain-source voltage 55 V
TO220AB and SOT404 . Using I
D
Drain current (DC) 13 A
’trench’ technology which features P
tot
Total power dissipation 53 W
very low on-state resistance. It is T
j
Junction temperature 175 ˚C
intended for use in automotive and R
DS(ON)
Drain-source on-state
general purpose switching resistance V
GS
= 5 V 150 mΩ
applications. V
GS
= 10 V 137 mΩ
PINNING
TO220AB & SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
tab/mb drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage - - 55 V
V
DGR
Drain-gate voltage R
GS
= 20 kΩ -55V
±V
GS
Gate-source voltage - - 10 V
±V
GSM
Non-repetitive gate-source voltage t
p
≤50µS - 15 V
I
D
Drain current (DC) T
mb
= 25 ˚C - 13 A
I
D
Drain current (DC) T
mb
= 100 ˚C - 9 A
I
DM
Drain current (pulse peak value) T
mb
= 25 ˚C - 53 A
P
tot
Total power dissipation T
mb
= 25 ˚C - 53 W
T
stg
, T
j
Storage & operating temperature - - 55 175 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction to - - 2.8 K/W
mounting base
R
th j-a
Thermal resistance junction to in free air 60 - K/W
ambient(TO220AB)
R
th j-a
Thermal resistance junction to Minimum footprint, FR4 50 - K/W
ambient(SOT404) board
123
tab
13
mb
2
SOT404
TO220AB
d
g
s
February 2000 1 Rev 1.000
Philips Semiconductors Product specification
TrenchMOS transistor BUK95150-55A
Logic level FET BUK96150-55A
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown V
GS
= 0 V; I
D
= 0.25 mA; 55 - - V
voltage T
j
= -55˚C 50 - - V
V
GS(TO)
Gate threshold voltage V
DS
= V
GS
; I
D
= 1 mA 1 1.5 2.0 V
T
j
= 175˚C 0.5 - - V
T
j
= -55˚C - - 2.3 V
I
DSS
Zero gate voltage drain current V
DS
= 55 V; V
GS
= 0 V; - 0.05 10 µA
T
j
= 175˚C - - 500 µA
I
GSS
Gate source leakage current V
GS
= ±10 V; V
DS
= 0 V - 2 100 nA
R
DS(ON)
Drain-source on-state V
GS
= 5 V; I
D
= 13 A - 125 150 mΩ
resistance T
j
= 175˚C - - 300 mΩ
V
GS
= 10 V; I
D
= 13 A - 116 137 mΩ
V
GS
= 4.5 V; I
D
= 13 A - 124 161 mΩ
DYNAMIC CHARACTERISTICS
T
mb
= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
C
iss
Input capacitance V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz - 254 339 pF
C
oss
Output capacitance - 54 65 pF
C
rss
Feedback capacitance - 42 58 pF
t
d on
Turn-on delay time V
DD
= 30 V; R
load
=1.2Ω;-66ns
t
r
Turn-on rise time V
GS
= 5 V; R
G
= 10 Ω - 285 428 ns
t
d off
Turn-off delay time - 1 1.4 ns
t
f
Turn-off fall time - 18 25 ns
L
d
Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die
L
d
Internal drain inductance Measured from contact screw on - 3.5 - nH
tab to centre of die(TO220AB)
L
d
Internal drain inductance Measured from upper edge of drain - 2.5 - nH
tab to centre of die(SOT404)
L
s
Internal source inductance Measured from source lead to - 7.5 - nH
source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
DR
Continuous reverse drain - - 13 A
current
I
DRM
Pulsed reverse drain current - - 53 A
V
SD
Diode forward voltage I
F
= 25 A; V
GS
= 0 V - 0.85 1.2 V
I
F
= 53 A; V
GS
= 0 V - 1.1 - V
t
rr
Reverse recovery time I
F
= 53 A; -dI
F
/dt = 100 A/µs; - 24 - ns
Q
rr
Reverse recovery charge V
GS
= -10 V; V
R
= 30 V - 0.026 - µC
February 2000 2 Rev 1.000
Philips Semiconductors Product specification
TrenchMOS transistor BUK95150-55A
Logic level FET BUK96150-55A
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
W
DSS
1
Drain-source non-repetitive I
D
= 8 A; V
DD
≤ 25 V; - - 25 mJ
unclamped inductive turn-off V
GS
= 5 V; R
GS
= 50 Ω; T
mb
= 25 ˚C
energy
!
Fig.1. Normalised power dissipation.
PD% = 100⋅P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100⋅I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥ 5 V
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
0 20 40 60 80 100 120 140 160 180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1 10 100
1
10
100
1000
RDS(ON)=VSD/ID
DC
ID/A
VSD/V
tp=
10ms
1ms
100us
10us
1us
0 20 40 60 80 100 120 140 160 180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0.01
0.1
1
10
1E-07 1E-05 1E-03 1E-01 1E+01
t/s
Zth/(K/W)
0
0.02
0.05
0.1
0.2
0.5
1 For maximum permissible repetitive avalanche current see fig.18.
February 2000 3 Rev 1.000
P1-P3P4-P6P7-P9

BUK96150-55A,118

Mfr. #:
Buy BUK96150-55A,118
Manufacturer:
NXP Semiconductors
Description:
MOSFET N-CH 55V 13A D2PAK
Lifecycle:
New from this manufacturer.
Delivery:
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