BUK96150-55A,118

Philips Semiconductors Product specification
TrenchMOS transistor BUK95150-55A
Logic level FET BUK96150-55A
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.7. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(V
GS
); conditions: I
D
= 13 A;
Fig.8. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.9. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.10. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
0
10
20
30
40
50
60
70
80
90
100
0246810
VDS/V
ID/A
2.8
3.0
3.6
3.8
4.0
6.0
10.0
VGS/V =
2.6
3.4
3.2
2.4
4.4
4.8
5.0
5.5
6.5
7.0
7.5
0
10
20
30
40
50
60
70
01234567
VGS/V
ID/A
Tj/C= 175
o
C
25
o
C
0 10203040506070
20
25
30
35
40
ID/A
RDS(ON)/mOhm
VGS/V=
3.0
3.2
3.4
3.6
4.0
5.0
0
5
10
15
20
25
0 5 10 15 20 25 30 35
ID/A
gfs/S
345678910
22
23
24
25
26
27
28
29
30
31
32
33
ID/A
RDS(ON)/mOhm
0.5
1
1.5
2
2.5
3
-100 -50 0 50 100 150 200
Tmb / degC
a
Rds(on) normalised to 25degC
February 2000 4 Rev 1.000
Philips Semiconductors Product specification
TrenchMOS transistor BUK95150-55A
Logic level FET BUK96150-55A
Fig.11. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.12. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.13. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.14. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 25 A; parameter V
DS
Fig.15. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.16. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 75 A
-100 -50 0 50 100 150 200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
0
1
2
3
4
5
0 5 10 15 20
QG / nC
VGS / V
VDS = 14V
VDS = 44V
0
10
20
30
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0
VSDS/V
IF/A
25
o
C
Tj/C= 150
o
C
0 0.5 1 1.5 2 2.5 3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
2% typ
98%
20 40 60 80 100 120 140 160 180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
0.0
0.5
1.0
1.5
2.0
2.5
0.01 0.1 1 10 100
VDS/V
Ciss
Coss
Crss
Capacitance / nF
February 2000 5 Rev 1.000
Philips Semiconductors Product specification
TrenchMOS transistor BUK95150-55A
Logic level FET BUK96150-55A
Fig.17. Avalanche energy test circuit.
Fig.18. Maximum permissible repetitive avalanche
current(I
AV
) versus avalanche time(t
AV
) for unclamped
inductive loads.
Fig.19. Switching test circuit.
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
RD
T.U.T.
VDD
RG
VDS
+
-
VGS
0
W
DSS
= 0.5 LI
D
2
BV
DSS
/(BV
DSS
V
DD
)
1
10
100
0.001 0.01 0.1 1 10
Avalanche Time, t
AV
(ms)
I
AV
T
j
prior to avalanche 150
o
C
25
o
C
February 2000 6 Rev 1.000

BUK96150-55A,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
MOSFET N-CH 55V 13A D2PAK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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