© Semiconductor Components Industries, LLC, 2009
September, 2009 − Rev. 1
1 Publication Order Number:
NTMD4840N/D
NTMD4840N
Power MOSFET
30 V, 7.5 A, Dual N−Channel, SOIC−8
Features
• Low R
DS(on)
to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• Dual SOIC−8 Surface Mount Package Saves Board Space
• This is a Pb−Free Device
Applications
• Disk Drives
• DC−DC Converters
• Printers
MAXIMUM RATINGS (T
J
= 25°C unless otherwise stated)
Rating
Symbol Value Unit
Drain−to−Source Voltage V
DSS
30 V
Gate−to−Source Voltage V
GS
±20 V
Continuous Drain
Current R
q
JA
(Note 1)
Steady
State
T
A
= 25°C
I
D
5.5
A
T
A
= 70°C 4.4
Power Dissipation
R
q
JA
(Note 1)
T
A
= 25°C P
D
1.14 W
Continuous Drain
Current R
q
JA
(Note 2)
T
A
= 25°C
I
D
4.5
A
T
A
= 70°C 3.5
Power Dissipation
R
q
JA
(Note 2)
T
A
= 25°C P
D
0.68 W
Continuous Drain
Current R
q
JA
t < 10 s
(Note 1)
T
A
= 25°C
I
D
7.5
A
T
A
= 70°C 6.0
Power Dissipation
R
q
JA
t < 10 s (Note 1)
T
A
= 25°C P
D
1.95 W
Pulsed Drain Current T
A
= 25°C,
t
p
= 10 ms
I
DM
30 A
Operating Junction and Storage Temperature T
J
, T
STG
−55 to
+150
°C
Source Current (Body Diode) I
S
2.0 A
Single Pulse Drain−to−Source Avalanche
Energy T
J
= 25°C, V
DD
= 30 V, V
GS
= 10 V,
I
L
= 7.5 A
pk
, L = 1.0 mH, R
G
= 25 W
EAS 28 mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260 °C
THERMAL RESISTANCE RATINGS
Rating Symbol Max Unit
Junction−to−Ambient – Steady State (Note 1)
R
q
JA
110
°C/W
Junction−to−Ambient – t≤10 s (Note 1)
R
q
JA
64
Junction−to−FOOT (Drain)
R
q
JF
40
Junction−to−Ambient – Steady State (Note 2)
R
q
JA
183.5
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 inch sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
http://onsemi.com
N−Channel
30 V
36 mW @ 4.5 V
24 mW @ 10 V
R
DS(on)
Max
I
D
Max
V
(BR)DSS
7.5 A
Device Package Shipping
†
ORDERING INFORMATION
NTMD4840NR2G SOIC−8
(Pb−Free)
2500/Tape & Reel
SOIC−8
CASE 751
STYLE 11
4840N = Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
8
4840N
AYWW
G
1
8
MARKING DIAGRAM
& PIN ASSIGNMENT
S1 G1 S2 G2
D1 D1 D2 D2
D
G
S