102006 Semtech Corp. www.semtech.com
SC4808B-1
POWER MANAGEMENT
age divider provides a 3X amplification of the CS signal.
This is used for comparison to the external error amplifier
signal. If an external resistor is connected from CS to the
current sense resistor, the internal current source will pro-
vide a programmable slope compensation. The value of
the resistor will determine the level of compensation. At
higher compensation levels, voltage mode of operation can
be achieved. The error amplifier signal at the FB pin will be
used in conjunction with the CS signal to achieve regula-
tion.
Two levels of undervoltage lockout are also available. The
LUVLO (line under voltage lockout) pin via an external re-
sistive divider will program the undervoltage lockout level.
During the LUVLO, the driver outputs are disabled and the
softstart is reset.
Once VCC has exceeded the UVLO (VCC under voltage lock-
out) limit, the internal reference, oscillator, drivers and logic
are powered up.
SYNC is a positive edge triggered input with a threshold
set to 1.0V.
By connecting an external control signal to the SYNC pin,
the internal oscillator frequency will be synchronized to the
positive edge of the external control signal. In a single con-
troller operation, SYNC should be grounded or connected
to an external synchronization clock within the SYNC fre-
quency range (see page 3).
In the Bi-phase operation mode a very unique oscillator
is utilized to allow two SC4808B-1 to be synchronized
together and work out of phase. This feature is setup by
simple connection of the SYNC input to the RC pin of the
other part. The fastest oscillator automatically becomes
the master, forcing the two PWMs to operate out of
phase. This feature minimizes the input and output
ripples, and reduces stress on the capacitors.
THEORY OF OPERATION
The SC4808B-1 is a versatile double ended, high speed,
low power, pulse width modulator that is optimized for ap-
plications requiring minimum space.
The device contains all of the control and drive circuity re-
quired for isolated or non isolated power supplies where
an external error amplifier is used. A fixed oscillator fre-
quency (up to 1MHz) can be programmed by an external
RC network.
The SC4808B-1 is a peak current or voltage mode
controller, depending on the amount of slope
compensation, programmable with only one external
resistor. The cycle by cycle peak current limit prevents core
saturation when a transformer is used for isolation while
the overcurrent circuitry initiates the softstart cycle.
The SC4808B-1 dual output drive stages are arranged in a
push-pull configuration. Both outputs switch at half the
oscillator frequency using a toggle flip flop. The dead time
between the two outputs is programmable depending on
the values of the timing capacitor and resistors, thus limiting
each output stage duty cycle to less than 50%.
The SC4808B-1 also provides flexibility with programmable
LUVLO thresholds, with built-in hysteresis.
SUPPLY
A single supply, VCC is used to provide the bias for the
internal reference, oscillator, drivers, and logic circuitry of
SC4808B-1. To ensure proper operation during start up,
VCC slew rate of less than 10V/mS is recommended.
PWM CONTROLLER
SC4808B-1 is a double ended PWM controller that can be
used in voltage or current mode applications. The
SC4808B-1 provides a 4.4V VCC UVLO, and a 3.125V ref-
erence. The oscillator frequency is programmed by a resis-
tor and a capacitor network connected to an external refer-
ence provided by the SC4808B-1. The two outputs, OUTA
and OUTB, are 180 degrees out of phase and run at half of
the oscillator frequency.
An external error amplifier will provide the error signal to
the FB pin of the SC4808B-1.
The current sense input and internal slope compensation
are both provided via the CS pin. The current sense input
from a sense resistor is used for the peak current and
overcurrent comparators. An internal 1 to 3 feedback volt-
Application Information
112006 Semtech Corp. www.semtech.com
SC4808B-1
POWER MANAGEMENT
VCC UNDER VOLTAGE LOCK OUT
Depending on the application and the voltages available,
the SC4808B-1 (UVLO = 4.4V) can be used to provide the
VCC undervoltage lock out function to ensure the convert-
ers controlled start up.
Before the VCC UVLO has been reached, the internal refer-
ence, oscillator, OUTA/OUTB drivers, and logic are disabled.
LINE UNDER VOLTAGE LOCK OUT
The SC4808B-1 also provides a line undervoltage (LUVLO
= Vref) function. The LUVLO pin is programmed via an ex-
ternal resistor divider connected as shown below. The ac-
tual start-up voltage can be calculated by using the equa-
tion below:
()
33R
33R23R
VV
REFStartup
+
×=
R27
15k
R24 10k
200p
C31
VCC
R26
2.2k
R28
10
2.2u,16V
C26
82p
C29
15
REF
0.1u,25V
C33
R25 18
R33
10k
SYNC
U4
SC4808
4
5
3
2
101
6
7
8
9
FB
REF
CS
RC
LUVLOSYNC
GND
OUTB
OUTA
VCC
R23
56.2k
Vin
REFERENCE
A 3.125V(SC4808B-1) reference voltage is available that
can be used to source a typical current of 5mA to the ex-
ternal circuitry. The Vref can be used to provide the oscilla-
tor RC network with a regulated bias.
Application Information (Cont.)
OSCILLATOR
The oscillator frequency is set by connecting a RC network
as shown below.
0
R27
15k
0
200p
C31
VCC
R28
10
2.2u,16V
C26
REF
0.1u,25V
C33
R33
10k
SYNC
U4
SC4808
4
5
3
2
101
6
7
8
9
FB
REF
CS
RC
LUVLOSYNC
GND
OUTB
OUTA
VCC
R23
56.2k
Vin
The oscillator has a ramp voltage of about Vref/2. The os-
cillator frequency is twice the frequency of the OUTA and
OUTB gate drive controls.
The oscillator capacitor C31 is charged by a current sourced
from the Vref through R27. Once the RC pin reaches about
Vref/2, the capacitor is discharged internally by the
SC4808B-1. It should be noted that larger capacitor val-
ues will result in a longer dead time during the down slope
of the ramp.
The following equation can be used as an approximation
of the oscillator frequency and the Dead time:
8.0
1
_
×
TOTOSC
AOSC
CR
F
9.0
1
_
×
TOTOSC
BOSC
CR
F
where:
CircuitSCOSCTOT
CCCC ++=
4808
pFC
SC
22
4808
3
103
5.0
××
REFOSC
deadtime
VC
T
The recommended range of timing resistors is between 10
kohm and 200kohm, range of timing capacitors is between
100pF and 1000pF. Timing resistors less than 10 kohm
should be avoided.
122006 Semtech Corp. www.semtech.com
SC4808B-1
POWER MANAGEMENT
SYNC/Bi-Phase operation
In noise sensitive applications where synchronization of
the oscillator frequency to a reference frequency is required,
the SYNC pin can accept the external clock. By connecting
an external control signal to the SYNC pin, the internal os-
cillator frequency will be synchronized to the positive edge
of the external control signal. SYNC is a positive edge trig-
gered input with a threshold set to 1.0V (SC4808B-1).
In a single controller operation, SYNC should be grounded
or connected to an external synchronization clock within
the SYNC frequency range (see page 3).
U2
SC4808
4
5
3
2
101
6
7
8
9
FB
REF
CS
RC
LUVLOSYNC
GND
OUTB
OUTA
VCC
Cosc1
U1
SC4808
4
5
3
2
101
6
7
8
9
FB
REF
CS
RC
LUVLOSYNC
GND
OUTB
OUTA
VCC
REF
Rosc2
REF
Rosc1
Cosc2
In the Bi-phase operation mode a very unique oscillator is
utilized to allow two SC4808B-1’s to be synchronized
together and work out of phase. This feature is set up by a
simple connection of the SYNC input to the RC pin of the
other part. The fastest oscillator automatically becomes
the master, forcing the two PWMs to operate out of phase.
This feature minimizes the input and output ripples, and
reduces stress on the capacitors.
Application Information (Cont.)
FEED BACK
The error signal from the output of an external error ampli-
fier such as SC431 or SC4431 is applied to the inverting
input of the PWM comparator at the FB pin either directly
or via an opto coupler for the isolated applications. For best
stability, keep the FB trace length as short as possible.
C39
22n
C38
0.1u
Vref
SC4431
1
2
4
5
R35C36
C35
R34
R36
R38
C37
R32
VoutVout
C40
22pF
R37
2.2k
MOCD207
3
4
6
5
Vref
FB
The signal at the FB pin is then compared to the 3X ampli-
fied signal from the current sense/ slope compensation
CS pin. Matched out of phase signals are generated to
control the OUTA and OUTB gate drives of the two phases.
A single ramp signal is used to generate the control sig-
nals for both phases, hence achieving a tightly matched
per phase operation.
Voltages below 1.5V at the FB pin, will produce a 0% duty
cycle at the OUTA/OUTB gate drives. This offset is to pro-
vide enough head room for the opto coupler used in iso-
lated applications.
GATE DRIVERS
OUTA and OUTB are out of phase bipolar gate drive output
stages, that are supplied from VCC and provide a peak
source/sink current of about 100mA. Both stages are ca-
pable of driving the logic input of external MOSFET drivers
or a NPN/PNP transistor buffer. The output stages switch
at half the oscillator frequency. When the voltage on the
RC pin is rising, one of the two outputs is high, but during
fall time, both outputs are off. This “dead time” between
the two outputs, along with a slower output rise and fall
time, insures that the two outputs can not be on at the
same time. The dead time is programmable and depends
upon the timing capacitor.
OUTA (PWM1)
OUTB (PWM1)
OUTA (PWM2)
OUTB (PWM2)

SC4808B-1MSTRT

Mfr. #:
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Semtech
Description:
IC REG CTRLR MULT TOP 10MSOP
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