5 2006 Semtech Corp. www.semtech.com
SC4808B-1
POWER MANAGEMENT
FB: The inverting input to the PWM comparator. Stray in-
ductances and parasitic capacitance should be minimized
by utilizing ground planes and correct layout guide lines
(see page 19).
REF: Bandgap reference output It should be by passed with
a 2.2uF low ESR capacitance, right at the IC pin.
CS: Current sense input and internal slope compensation
are both provided via the CS pin. The current sense input
from a sense resistor is used for the peak current and
overcurrent comparators. An internal 1 to 3 feed back volt-
age divider provides a 3X amplification of the CS signal.
This is used for comparison to the external error amplifier
signal. If an external resistor is connected from CS to the
current sense resistor, the internal current source will pro-
vide a programmable slope compensation. The value of
the resistor will determine the level of compensation. At
higher compensation levels, voltage mode of operation can
be achieved.
RC: The oscillator programming pin. The oscillator should
be referenced to a stable reference voltage for an accu-
rate and stable frequency. Only two components are re-
quired to program the oscillator, a resistor (tied to Vref and
RC), and a capacitor (tied to the RC and GND). The follow-
ing formula can be used for a close approximation of the
oscillator frequency.
8.0
1
_
×
≅
TOTOSC
AOSC
CR
F
9.0
1
_
×
≅
TOTOSC
BOSC
CR
F
where:
CircuitSCOSCTOT
CCCC ++=
4808
pFC
SC
22
4808
≅
Where the frequency is in Hertz, resistance in ohms, and
capacitance in farads. The recommended range of timing
resistors is between 10 kohm and 200kohm and range of
timing capacitors is between 100pF and 1000pF. Timing
resistors less than 10 kohm should be avoided.
Refer to layout guide lines on (page 19) to achieve best
results.
LUVLO: Line undervoltage lockout pin. An external resis-
tive divider will program the undervoltage lockout level. The
external divider should be referenced to the quiet analog
ground (see page 19). During the LUVLO, the driver out-
puts are disabled and the softstart is reset. This pin can
also function as an Enable/Disable.
SYNC: SYNC is a positive edge triggered input with a thresh-
old set to 1.0V. In a single controller operation, SYNC could
be grounded or connected to an external synchronization
clock within the SYNC frequency range (see page 3). In
the Bi-Phase operation mode SYNC pins could be con-
nected to the Cosc (Timing Capacitors) of the other con-
troller. This will force an out of phase operation (see page
12).
GND: Device power and analog ground. Careful attention
should be paid to the layout of the ground planes (see page
19).
OUTA and OUTB: Out of phase gate drive stages. The
driver’s peak source and sink current drive capability of
100mA, enables the use of an external MOSFET driver or
a NPN/PNP transistor buffer.
The oscillator RC network programs the oscillator frequency,
which is twice the OUTA/OUTB frequency. To insure that
the outputs do not overlap, a dead time can be generated
between the two outputs by sizing the oscillator timing
capacitor (see page 11).
VCC: The supply input for the device. Once VCC has ex-
ceeded the UVLO limit, the internal reference, oscillator,
drivers and logic are powered up. A low ESR capacitance,
should be used for decoupling right at the IC pin to mini-
mize noise problems.
Pin Descriptions
