AD7863
Rev. B | Page 9 of 24
CONVERTER DETAILS
The AD7863 is a high speed, low power, dual 14-bit analog-to-
digital converter that operates from a single 5 V supply. The
part contains two 5.2 μs successive approximation ADCs, two
track-and-hold amplifiers, an internal 2.5 V reference, and a
high speed parallel interface. Four analog inputs are grouped
into two channels (A and B) selected by the A0 input. Each
channel has two inputs (V
A1
and V
A2
or V
B1
and V
B2
) that can be
sampled and converted simultaneously, thus preserving the
relative phase information of the signals on both analog inputs.
The part accepts an analog input range of ±10 V (AD7863-10),
±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). Overvoltage
protection on the analog inputs for the part allows the input
voltage to go to ±17 V, ±7 V, or +7 V, respectively, without
causing damage. The AD7863 has two operating modes, the high
sampling mode and the auto sleep mode, where the part auto-
matically goes into sleep after the end of conversion. These modes
are discussed in more detail in the Timing and Control section.
Conversion is initiated on the AD7863 by pulsing the
CONVST
input. On the falling edge of
CONVST
, both on-chip track-and-
holds are simultaneously placed into hold and the conversion
sequence is started on both channels. The conversion clock for
the part is generated internally using a laser-trimmed clock
oscillator circuit. The BUSY signal indicates the end of
conversion and at this time the conversion results for both
channels are available to be read. The first read after a conver-
sion accesses the result from V
A1
or V
B1
, and the second read
accesses the result from V
A2
or V
B2
, depending on whether the
multiplexer select A0 is low or high, respectively, before the
conversion is initiated. Data is read from the part via a 14-bit
parallel data bus with standard
CS
and
RD
signals.
Conversion time for the AD7863 is 5.2 μs in the high sampling
mode (10 μs for the auto sleep mode), and the track/hold
acquisition time is 0.5 μs. To obtain optimum performance
from the part, the read operation should not occur during the
conversion or during the 400 ns prior to the next conversion.
This allows the part to operate at throughput rates up to 175 kHz
and achieve data sheet specifications.
TRACK-AND-HOLD SECTION
The track-and-hold amplifiers on the AD7863 allow the ADCs
to accurately convert an input sine wave of full-scale amplitude
to 14-bit accuracy. The input bandwidth of the track-and-hold
is greater than the Nyquist rate of the ADC, even when the
ADC is operated at its maximum throughput rate of 175 kHz
(that is, the track-and hold can handle input frequencies in
excess of 87.5 kHz).
The track-and-hold amplifiers acquire input signals to 14-bit
accuracy in less than 500 ns. The operation of the track-and-
holds is essentially transparent to the user. The two track-and-hold
amplifiers sample their respective input channels simultaneously,
on the falling edge of
CONVST
. The aperture time for the
track-and-holds (that is, the delay time between the external
CONVST
signal and the track-and-hold actually going into
hold) is well-matched across the two track-and-holds on one
device and also well-matched from device to device. This allows
the relative phase information between different input channels
to be accurately preserved. It also allows multiple AD7863s to
simultaneously sample more than two channels. At the end of
conversion, the part returns to its tracking mode. The acquisition
time of the track-and-hold amplifiers begins at this point.
REFERENCE SECTION
The AD7863 contains a single reference pin, labeled V
REF
, that
provides access to the part’s own 2.5 V reference. Alternatively,
an external 2.5 V reference can be connected to this pin, thus
providing the reference source for the part. The part is specified
with a 2.5 V reference voltage. Errors in the reference source
result in gain errors in the AD7863 transfer function and add to
the specified full-scale errors on the part. On the AD7863-10
and AD7863-3, it also results in an offset error injected in the
attenuator stage.
The AD7863 contains an on-chip 2.5 V reference. To use this
reference as the reference source for the AD7863, connect two
0.1 μF disc ceramic capacitors from the V
REF
pin to AGND. The
voltage that appears at this pin is internally buffered before
being applied to the ADC. If this reference is required for use
external to the AD7863, it should be buffered because the part
has a FET switch in series with the reference output resulting in
a source impedance for this output of 5.5 kΩ nominal. The
tolerance on the internal reference is ±10 mV at 25°C with a
typical temperature coefficient of 25 ppm/°C and a maximum
error over temperature of ±25 mV.
If the application requires a reference with a tighter tolerance or
the AD7863 needs to be used with a system reference, the user
has the option of connecting an external reference to this V
REF
pin. The external reference effectively overdrives the internal
reference and thus provides the reference source for the ADC.
The reference input is buffered before being applied to the ADC
with a maximum input current of ±100 μA. A suitable reference
source for the AD7863 is the AD780 precision 2.5 V reference.
AD7863
Rev. B | Page 10 of 24
CIRCUIT DESCRIPTION
ANALOG INPUT SECTION
The AD7863 is offered as three part types: the AD7863-10,
which handles a ±10 V input voltage range, the AD7863-3,
which handles input voltage range ±2.5 V and the AD7863-2,
which handles a 0 V to 2.5 V input voltage range.
2.5V
REFERENCE
MUX
R2
R1
R3
TO INTERNAL
COMPARATOR
TRACK/
HOLD
V
REF
V
AX
AGND
AD7863-10/AD7863-3
2k
TO ADC
REFERENCE
CIRCUITRY
06411-005
Figure 5. AD7863-10/AD7863-3 Analog Input Structure
Figure 5 shows the analog input section for the AD7863-10 and
AD7863-3. The analog input range of the AD7863-10 is ±10 V
into an input resistance of typically 9 kΩ. The analog input
range of the AD7863-3 is ±2.5 V into an input resistance of
typically 3 kΩ. This input is benign, with no dynamic charging
currents because the resistor stage is followed by a high input
impedance stage of the track-and-hold amplifier. For the
AD7863-10, R1 = 8 kΩ, R2 = 2 kΩ and R3 = 2 kΩ. For the
AD7863-3, R1 = R2 = 2 kΩ and R3 is open circuit.
For the AD7863-10 and AD7863-3, the designed code
transitions occur on successive integer LSB values (that is, 1 LSB,
2 LSBs, 3 LSBs . . .). Output coding is twos complement binary
with 1 LSB = FS/16,384. The ideal input/output transfer
function for the AD7863-10 and AD7863-3 is shown in
Table 5.
Table 5. Ideal Input/Output Code (AD7863-10/AD7863-3)
Analog Input
1
Digital Output Code Transition
+FSR/2 − 1 LSB
2
011 . . . 110 to 011 . . . 111
+FSR/2 − 2 LSBs 011 . . . 101 to 011 . . . 110
+FSR/2 − 3 LSBs 011 . . . 100 to 011 . . . 101
GND + 1 LSB 000 . . . 000 to 000 . . . 001
GND 111 . . . 111 to 000 . . . 000
GND − 1 LSB 111 . . . 110 to 111 . . . 111
−FSR/2 + 3 LSBs 100 . . . 010 to 100 . . . 011
−FSR/2 + 2 LSBs 100 . . . 001 to 100 . . . 010
−FSR/2 + 1 LSB 100 . . . 000 to 100 . . . 001
1
FSR is full-scale range = 20 V (AD7863-10) and = 5 V (AD7863-3) with V
REF
= 2.5 V.
2
1 LSB = FSR/16,384 = 1.22 mV (AD7863-10) and 0.3 mV (AD7863-3) with
V
REF
= 2.5 V.
The analog input section for the AD7863-2 contains no biasing
resistors and the V
AX/BX
pin drives the input directly to the
multiplexer and track-and-hold amplifier circuitry. The analog
input range is 0 V to 2.5 V into a high impedance stage with an
input current of less than 100 nA. This input is benign, with no
dynamic charging currents. Once again, the designed code
transitions occur on successive integer LSB values. Output
coding is straight (natural) binary with 1 LSB = FS/16,384 =
2.5 V/16,384 = 0.15 mV.
Table 6 shows the ideal input/output
transfer function for the AD7863-2.
Table 6. Ideal Input/Output Code (AD7863-2)
Analog Input
1
Digital Output Code Transition
+FSR − 1 LSB
2
111 . . . 110 to 111 . . . 111
+FSR − 2 LSB 111 . . . 101 to 111 . . . 110
+FSR − 3 LSB 111 . . . 100 to 111 . . . 101
GND + 3 LSB 000 . . . 010 to 000 . . . 011
GND + 2 LSB 000 . . . 001 to 000 . . . 010
GND + 1 LSB 000 . . . 000 to 000 . . . 001
1
FSR is full-scale range = 2.5 V for AD7863-2 with V
REF
= 2.5 V.
2
1 LSB = FSR/16,384 = 0.15 mV for AD7863-2 with V
REF
= 2.5 V.
OFFSET AND FULL-SCALE ADJUSTMENT
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Invariably, some applications require that the
input signal span the full analog input dynamic range. In such
applications, offset and full-scale error have to be adjusted to zero.
Figure 6 shows a typical circuit that can be used to adjust the
offset and full-scale errors on the AD7863 (V
A1
on the
AD7863-10 version is shown for example purposes only).
Where adjustment is required, offset error must be adjusted
before full-scale error. This is achieved by trimming the offset
of the op amp driving the analog input of the AD7863 while the
input voltage is ½ LSB below analog ground. The trim
procedure is as follows: apply a voltage of −0.61 mV (−½ LSB)
at V
1
in Figure 6 and adjust the op amp offset voltage until the
ADC output code flickers between 11 1111 1111 1111 and
00 0000 0000 0000.
R2
500
*ADDITIONAL PINS OMITTED FOR CLARITY.
V
A1
AGND
AD7863*
R1
10k
R3
10k
R5
10k
R4
10k
V
1
INPUT RANGE = ±10
V
06411-006
Figure 6. Full-Scale Adjust Circuit
AD7863
Rev. B | Page 11 of 24
Gain error can be adjusted at either the first code transition (ADC
negative full scale) or the last code transition (ADC positive full
scale). The trim procedures for both cases are as follows:
Positive Full-Scale Adjust (−10 Version)
Apply a voltage of 9.9927 V (FS/2 – 1 LSBs) at V
1
. Adjust R2
until the ADC output code flickers between 01 1111 1111 1110
and 01 1111 1111 1111.
Negative Full-Scale Adjust (−10 Version)
Apply a voltage of −9.9976 V (−FS + 1 LSB) at V
1
. Adjust R2
until the ADC output code flickers between 10 0000 0000 0000
and 10 0000 0000 0001.
An alternative scheme for adjusting full-scale error in systems
that use an external reference is to adjust the voltage at the V
REF
pin until the full-scale error for any of the channels is adjusted
out. The good full-scale matching of the channels ensures small
full-scale errors on the other channels.
TIMING AND CONTROL
Figure 7 shows the timing and control sequence required to
obtain optimum performance (Mode 1) from the AD7863. In
the sequence shown, a conversion is initiated on the falling edge
of
CONVST
. This places both track-and-holds into hold
simultaneously and new data from this conversion is available
in the output register of the AD7863 5.2 μs later. The BUSY
signal indicates the end of conversion and at this time the
conversion results for both channels are available to be read. A
second conversion is then initiated. If the multiplexer select (A0)
is low, the first and second read pulses after the first conversion
accesses the result from Channel A (V
A1
and V
A2
, respectively).
The third and fourth read pulses, after the second conversion
and A0 high, accesses the result from Channel B (V
B1
and V
B2
,
respectively). The state of A0 can be changed any time after the
CONVST
goes high, that is, track-and-holds into hold and 500 ns
prior to the next falling edge of
CONVST
. Note that A0 should
not be changed during conversion if the nonselected channels
have negative voltages applied to them, which are outside the
input range of the AD7863, because this affects the conversion
in progress. Data is read from the part via a 14-bit parallel data
bus with standard
CS
and
RD
signal, that is, the read operation
consists of a negative going pulse on the
CS
pin combined with
two negative going pulses on the
RD
pin (while the
CS
is low),
accessing the two 14-bit results. Once the read operation has
taken place, a further 400 ns should be allowed before the next
falling edge of
CONVST
to optimize the settling of the track-
and-hold amplifier before the next conversion is initiated.
The achievable throughput rate for the part is 5.2 μs (conversion
time) plus 100 ns (read time) plus 0.4 μs (quiet time). This
results in a minimum throughput time of 5.7 μs (equivalent to
a throughput rate of 175 kHz).
V
A1
V
A2
V
B1
V
B2
C
ONVST
BUSY
A0
CS
RD
DATA
t
CONV
= 5.2µs
06411-007
t
3
t
8
t
ACQ
t
1
t
4
t
2
t
5
t
6
t
7
Figure 7. Mode 1 Timing Operation Diagram for High Sampling Performance

AD7863ARZ-10

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Simult Sampling Dual 175 kSPS 14-Bit
Lifecycle:
New from this manufacturer.
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