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AD7863ARZ-10

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
AD7863
Rev. B | Page 3 of 24
SPECIFICATIONS
V
DD
= 5 V ± 5%, AGND = DGND = 0 V, REF = Internal. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter A Version
1
B Version
1
Unit Test Conditions/Comments
SAMPLE AND HOLD
−3 dB Small Signal Bandwidth 7 7 MHz typ
Aperture Delay
2
35 35 ns max
Aperture Jitter
2
50 50 ps typ
Aperture Delay Matching
2
350 350 ps max
DYNAMIC PERFORMANCE
3
f
IN
= 80.0 kHz, f
S
= 175 kSPS
Signal-to-(Noise + Distortion) Ratio
4
@ 25°C 78 78 dB min
T
MIN
to T
MAX
77 77 dB min
Total Harmonic Distortion
4
−82 −82 dB max −87 dB typ
Peak Harmonic or Spurious Noise
4
−82 −82 dB max −90 dB typ
Intermodulation Distortion
4
fa = 49 kHz, fb = 50 kHz
Second Order Terms −93 −93 dB typ
Third Order Terms −89 −89 dB typ
Channel-to-Channel Isolation
4
−86 −86 dB typ f
IN
= 50 kHz sine wave
DC ACCURACY Any channel
Resolution 14 14 Bits
Minimum Resolution for Which No
Missing Codes are Guaranteed 14 14 Bits
Relative Accuracy
4
±2.5 ±2 LSB max
Differential Nonlinearity
4
+2 to −1 +2 to −1 LSB max
AD7863-10, AD7863-3
Positive Gain Error
4
±10 ±8 LSB max
Positive Gain Error Match
4
10 10 LSB max
Negative Gain Error
4
±10 ±8 LSB max
Negative Gain Error Match
4
10 10 LSB max
Bipolar Zero Error ±10 ±8 LSB max
Bipolar Zero Error Match 8 6 LSB max
AD7863-2
Positive Gain Error
4
±14 LSB max
Positive Gain Error Match
4
16 LSB max
Unipolar Offset Error ±14 LSB max
Unipolar Offset Error Match 10 LSB max
ANALOG INPUTS
AD7863-10
Input Voltage Range ±10 ±10 V
Input Resistance 9 9 kΩ typ
AD7863-3
Input Voltage Range ±2.5 ±2.5 V
Input Resistance 3 3 kΩ typ
AD7863-2
Input Voltage Range 2.5 2.5 V
Input Current 100 100 nA max
AD7863
Rev. B | Page 4 of 24
Parameter A Version
1
B Version
1
Unit Test Conditions/Comments
REFERENCE INPUT/OUTPUT
REF IN Input Voltage Range 2.375 to 2.625 2.375 to 2.625 V 2.5 V ± 5%
REF IN Input Current ±100 ±100 μA max
REF OUT Output Voltage 2.5 2.5 V nom
REF OUT Error @ 25°C ±10 ±10 mV max
REF OUT Error T
MIN
to T
MAX
±20 ±20 mV max
REF OUT Temperature Coefficient 25 25 ppm/°C typ
LOGIC INPUTS
Input High Voltage, V
INH
2.4 2.4 V min V
DD
= 5 V ± 5%
Input Low Voltage, V
INL
0.8 0.8 V max V
DD
= 5 V ± 5%
Input Current, I
IN
±10 ±10 μA max
Input Capacitance, C
IN
5
10 10 pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
4.0 4.0 V min I
SOURCE
= 200 μA
Output Low Voltage, V
OL
0.4 0.4 V max I
SINK
= 1.6 mA
DB11 to DB0
Floating-State Leakage Current ±10 ±10 μA max
Floating-State Capacitance
5
10 10 pF max
Output Coding
AD7863-10, AD7863-3 Twos complement
AD7863-2 Straight (natural) binary
CONVERSION RATE
Conversion Time
Mode 1 Operation 5.2 5.2 μs max For both channels
Mode 2 Operation
6
10.0 10.0 μs max For both channels
Track/Hold Acquisition Time
4, 7
0.5 0.5 μs max
POWER REQUIREMENTS
V
DD
5 5 V nom ±5% for specified performance
I
DD
Normal Mode (Mode 1)
AD7863-10 18 18 mA max
AD7863-3 16 16 mA max
AD7863-2 11 11 mA max
Power-Down Mode (Mode 2)
I
DD
@ 25°C
8
20 20 μA max 40 nA typ. Logic inputs = 0 V or V
DD
Power Dissipation
Normal Mode (Mode 1)
AD7863-10 94.50 94.50 mW max V
DD
= 5.25 V, 70 mW typ
AD7863-3 84 84 mW max V
DD
= 5.25 V, 70 mW typ
AD7863-2 57.75 57.75 mW max V
DD
= 5.25 V, 45 mW typ
Power-Down Mode @ 25°C 105 105 μW max 210 nW typ, V
DD
= 5.25 V
1
Temperature ranges are as follows: A Version and B Version, −40°C to +85°C.
2
Sample tested during initial release.
3
Applies to Mode 1 operation. See Operating Modes section.
4
See Terminology section.
5
Sample tested @ 25°C to ensure compliance.
6
This 10 μs includes the wake-up time from standby. This wake-up time is timed from the rising edge of
CONVST
, whereas conversion is timed from the falling edge of
CONVST
, for a narrow
CONVST
pulse width the conversion time is effectively the wake-up time plus conversion time, 10 μs. This can be seen from Figure 6. Note that if
the
CONVST
pulse width is greater than 5.2 μs, the effective conversion time increases beyond 10 μs.
7
Performance measured through full channel (multiplexer, SHA, and ADC).
8
For best dynamic performance of the AD7863, ATE device testing has to be performed with power supply decoupling in place. In the AD7863 power-down mode of
operation, the leakage current associated with these decoupling capacitors is greater than that of the AD7863 supply current. Therefore, the 40 nA typical figure
shown is characterized and guaranteed by design figure, which reflects the supply current of the AD7863 without decoupling in place. The maximum figure shown in
the Conditions/Comments column reflects the AD7863 with supply decoupling in place—0.1 μF in parallel with 10 μF disc ceramic capacitors on the V
DD
pin and
2 × 0.1 μF disc ceramic capacitors on the V
REF
pin, in both cases to the AGND plane.
AD7863
Rev. B | Page 5 of 24
TIMING CHARACTERISTICS
V
DD
= 5 V ± 5%, AGND = DGND = 0 V, REF = Internal. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1, 2
A, B Versions Unit Test Conditions/Comments
t
CONV
5.2 μs max Conversion time
t
ACQ
0.5 μs max Acquisition time
Parallel Interface
t
1
0 ns min
CS to RD setup time
t
2
0 ns min
CS to RD hold time
t
3
35 ns min
CONVST pulse width
t
4
45 ns min
RD pulse width
t
5
3
30 ns min
Data access time after falling edge of
RD
t
6
4
5 ns min
Bus relinquish time after rising edge of
RD
30 ns max
t
7
10 ns min Time between consecutive reads
t
8
400 ns min Quiet time
1
Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figure 2.
3
Measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
V
A1
V
A2
V
B1
V
B2
CONVST
BUSY
A0
CS
RD
DATA
t
CONV
= 5.2µs
06411-002
t
3
t
8
t
ACQ
t
1
t
4
t
2
t
5
t
6
t
7
Figure 2. Timing Diagram
TO OUTPUT
PIN
1.6mA
200µA
50pF
06411-003
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD7863ARZ-10

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Buy AD7863ARZ-10
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Simult Sampling Dual 175 kSPS 14-Bit
Lifecycle:
New from this manufacturer.
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