MAX6621AUB+ Datasheet MAX6621AUB+, MAX6621AUB+T | P13-P15

The result is a 16-bit word (low byte transmitted first,

high byte second) that contains the register that

caused ALERT to assert. An error (8103h) is returned

when there is no active ALERT.

RESET

The MAX6621 features a power-on reset (POR), bus

lockout reset, and a reset input (RESET). The power-on

reset monitors V

and holds all outputs in high imped-

ance until V

passes the POR threshold. The

MAX6621 monitors V

for brownout conditions even

after power-up.

Bus Lockout Timeout Reset

If an I

C transaction starts and gets locked up for

greater than 20ms, the MAX6621 asserts the internal

bus lockup reset that restarts itself in the default startup

condition.

RESET

Input

The MAX6621 features a RESET input that allows users

to directly reset to the default startup conditions. Pull

RESET low for a minimum of 10ns for a valid reset. The

MAX6621 requires 100μs to be accessible after RESET

has been asserted.

Version Information Command

Table 18 shows the command to read the firmware version.

The result is a 16-bit word (low byte transmitted first,

high byte second), e.g., 0100h for the MAX6621 firmware

version 1.0.

Serial Interface

The MAX6621 operates as a slave that sends and

receives data through an I

C-compatible, 2-wire inter-

face. The interface uses a serial-data line (SDA) and a

serial-clock line (SCL) to achieve bidirectional commu-

nication between master and slave. A master (typically

a microcontroller) initiates all data transfers to and from

the MAX6621 and generates the SCL clock that syn-

chronizes the data transfer (Figure 5).

The MAX6621 SCL and SDA lines operate as both

inputs and open-drain outputs. A pullup resistor is

required on SCL and SDA.

Each transmission consists of a START condition sent

by a master, followed by the MAX6621 7-bit slave

address, plus an R/W bit, one or more data bytes, and

finally a STOP condition (Figure 6). To write to a

MAX6621 register, a write transmission consists of a

START condition, followed by the MAX6621 7-bit slave

address plus R/W = 0, a register address byte, one

data byte, and finally a STOP condition. To read from a

MAX6621 register, a combined write and read trans-

missions are required. The first write transmission con-

sists of a START condition, followed by the MAX6621

7-bit slave address plus R/W = 0, a register address

byte, and finally a STOP condition that sets the register

to be read. The second read transmission consists of a

START condition, followed by the MAX6621 7-bit slave

address plus R/W = 1, one or more data bytes, and

finally a STOP condition that reads the data from the

MAX6621

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______________________________________________________________________________________ 13

COMMAND DESCRIPTION TYPE RESULT

09h

Get firmware

version

ReadWord 16 bit word

Table 18. Firmware Command

SDA

SCL

HD, STA

HIGH

SU, DAT

LOW

START

CONDITION

STOP

CONDITION

REPEATED START

CONDITION

START

CONDITION

HD, DAT

SU, STO

SU, STA

HD, STA

BUF

Figure 5. 2-Wire Serial-Interface Timing Details

MAX6621

specified register. These write and read transmissions

can be joined using a repeated START even though the

MAX6621 7-bit slave address needs to be present pre-

ceding the R/W bits.

Start and Stop Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master

has finished communicating with the slave, it issues a

STOP (P) condition by transitioning SDA from low to

high while SCL is high. The bus is then free for another

transmission (Figure 6).

Data Transfer and Acknowledge

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 7).

The acknowledge bit is a clocked 9th bit that the recipi-

ent uses to handshake receipt of each byte of data

(Figure 8). Thus, each byte transferred effectively

requires 9 bits. The master generates the 9th clock

pulse, and the recipient pulls down SDA during the

acknowledge clock pulse so that the SDA line is stable

low during the high period of the clock pulse. When the

master is transmitting to the MAX6621, the MAX6621

generates the acknowledge bit because the MAX6621

is the recipient. When the MAX6621 is transmitting to

the master, the master generates the acknowledge bit

because the master is the recipient.

Slave Address

The MAX6621 has a 7-bit long slave address (Figure 9).

The 8th bit following the 7-bit slave address is the R/W

bit. The R/W bit is low for a write command and high for

a read command.

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14 ______________________________________________________________________________________

SDA

SCL

START

CONDITION

STOP

CONDITION

Figure 6. Start and Stop Conditions

SDA

SCL

DATA LINE STABLE;

DATA VALID

CHANGE OF DATA

ALLOWED

Figure 7. Bit Transfer

SCL

SDA BY

TRANSMITTER

CLOCK PULSE

FOR ACKNOWLEDGEMENT

START

CONDITION

SDA BY

RECEIVER

12 89

Figure 8. Acknowledge

0 1 1 A2 A1 A0 ACK0

SDA

SCL

Figure 9. Slave Address

The first six bits of the MAX6621 slave address

(A6:A1) are always 010101. A0 is selected by con-

necting AD0 to GND or V

. The resulting addresses

are shown in Table 19. Other slave addresses may be

possible as factory options, allowing multiple devices

to be controlled independently from the same inter-

face. Contact microcontroller technical support at

https://support.maxim-ic.com/micro.

MAX6621

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______________________________________________________________________________________ 15

TYPICAL READ WORD COMMAND

PEC (PACKET ERROR CHECKSUM) ENABLED

PEC (PACKET ERROR CHECKSUM) DISABLED

MASTER

ADDR:7 W A CMD:8 A

MAX6621 ADDR:7 R A RESLO:8 A RESHI:8 A PEC:8

THE RESULT CONSISTS OF RESLO FOR THE 8 LEAST SIGNIFICANT BITS (LSBS) AND RESHI FOR THE 8 MOST SIGNIFICANT BITS (MSBS), RESULTING IN A 16-BIT WORD.

TEMPERATURE DATA AND ERROR CODES ARE GIVEN AS 16-BIT WORDS.

ADDR:7: 7-BIT ADDRESS FOLLOWED BY A READ (R = 1) OR WRITE (W = 0) BIT TO FORM THE 8-BIT ADDRESS USED IN THE I

C/SMBUS PROTOCOL.

P: I

C STOP CONDITION. SEE FIGURE 6.

S: I

C START CONDITION. SEE FIGURE 6.

A: ACK. THE PULSE ON THE 9th CLOCK CYCLE TO INDICATE ACKNOWLEDGE TRANSFER. SLAVE PULLS LOW TO GND AND MASTER PULLS TO SLAVE'S V

NA: NOT ACKNOWLEDGE

CMD: COMMAND BYTE

RESLO: LEAST SIGNIFICANT 8-BIT RESULT

RESHI: MOST SIGNIFICANT 8-BIT RESULT

MASTER

ADDR:7 W A CMD:8 A

MAX6621 ADDR:7 R A RESLO:8 A RESHI:8

TYPICAL WRITE WORD COMMAND

COMMAND WITH PEC (PACKET ERROR CHECKSUM)

COMMAND WITHOUT PEC (PACKET ERROR CHECKSUM)

MASTER

ADDR:7 W A CMD:8 AS

MASTER

INLO:8 A INHI:8 A

INHI:8 A P

PEC:8 A

ADDR:7 W A CMD:8 A INLO:8 A

Figure 10. Typical Read/Write Word Command

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MAX6621AUB+

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Translation - Voltage Levels MAX6621 PROTOCOL CONVERTER USOP PB

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MAX6621AUB+

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