CONFIG0
The CONFIG0 register holds a bit mask for sockets and
domains that are enabled for polling as well as a
polling delay (minimum delay between sets of polls)
and features enable/disable bits. Table 2 shows the
various options for CONFIG0.
The optional polling delay (bits 2:0) inserts after polling
the set of all sockets and domains that are enabled in
bits 15:8 with a minimal pause of 2.5ms between PECI
reads. After polling all enabled sockets and domains,
the device pauses PECI communications for the config-
ured time before starting to poll the set of enabled
sockets and domains again. Table 3 shows the various
polling delay options.
CONFIG1
The CONFIG1 register configures the maximum num-
ber of retries before aborting a PECI temperature read
as well as the originated (suggested) PECI bit time.
Table 4 shows the various options for CONFIG1.
MAX6621
PECI-to-I
2
C Translator
_______________________________________________________________________________________ 7
BIT(S) DESCRIPTION DEFAULT
15:8 Polling enable for sockets and domains 00h
15 1 = enable socket 3, domain 1 0
14 1 = enable socket 3, domain 0 0
13 1 = enable socket 2, domain 1 0
12 1 = enable socket 2, domain 0 0
11 1 = enable socket 1, domain 1 0
10 1 = enable socket 1, domain 0 0
9 1 = enable socket 0, domain 1 0
8 1 = enable socket 0, domain 0 0
7
1 = enable I
2
C bus lockup timeout
0 = disable timeout
1
6
1 = alternate data representation
0 = 16-bit data representation
0
5
1 = enable I
2
C packet error checksum
(PEC) on device return data
0 = disable PEC
1
4
1 = mask temperature alerts
0 = activate alerts
0
3 Reserved, set to 0 0
2:0 Poll delay, see Table 3 5
Table 2. CONFIG0 Register
POLL DELAY VALUE DELAY BETWEEN POLLS (ms)
0 Polling on request only
1 2.5
25
310
450
5 100 (default)
6 500
7 Reserved
Table 3. Polling Delay
BIT(S) DESCRIPTION DEFAULT
15:8
Originated PECI bit time
(before negotiation)
01h: RESERVED
14h…0FFh: CONFIG1[15:8] + 1μs
Minimum: 14h (= 21μs/47.62kHz)
Maximum: 0FFh (= 25s/3.906kHz)
02h
7:0
Maximum number of retries for PECI
transactions
03h
Table 4. CONFIG1 Register
MAX6621
PECI-to-I
2
C Translator
8 _______________________________________________________________________________________
CONFIG2
The CONFIG2 register holds the offset that is added to
all temperature return values that are not error codes.
The offset is enabled in CONFIG0, bit 6; +95°C is set
as 17C0h or 005Fh, depending on the data format. To
represent +95°C in 16-bit representation, convert
+95°C to binary using two’s complement and left-shift
six times. The MAX6621 automatically converts the off-
set value to the equivalent value when the data format
is changed. See Table 5 for the default offset and Table
6 for some example values.
When configured in CONFIG2, and the return code is not
an error code (see the
Error Codes
section), the device
adds the offset value stored in CONFIG2 to the return
value. For example, if the CPU’s thermal control circuit
activation point is at +95°C, CONFIG2 can be set to
+95°C (005Fh or 17C0h) and all return values are con-
verted to absolute temperatures. Note that the thermal
control circuit activation point is CPU specific. The offset
value is represented in the current data format.
CONFIG3
CONFIG3 register configures the temperature averaging
function. See the
Temperature Averaging
section for
more information. Table 7 shows the default settings.
Temperature Representation
Temperature data is formatted in 16-bit two’s comple-
ment representing a range from -512°C to +512°C in
steps of 1/64°C (Figure 1). Internally, the device always
uses the 16-bit data format. The temperature is given in
two’s complement and left-shifted so that the +1°C bit
is bit 6 (Figure 2). Temperatures can be represented
externally in alternate data format if fractional readings
are not needed. Table 8 shows some examples.
BIT(S) DESCRIPTION DEFAULT
15:0 Temperature offset 0000h
Table 5. CONFIG2 Register
BINARY
TEMP (°C) HEX
RESHI RESLO
0 0000h 0000 0000 0000 0000
+25 0640h 0000 0110 0100 0000
+50 0C80h 0000 1100 1000 0000
+75 12C0h 0001 0010 1100 0000
+95 17C0h 0001 0111 1100 0000
Table 6. Example Offset Values in 16-Bit
Temperature Representation
BIT(S) DESCRIPTION DEFAULT
15:8 Reserved, set to 0 00h
7:0 Averaging shift count, see formula 00h
Table 7. CONFIG3 Register
RESLO
1°C
1
4
1
2
°C °C °C
°C °C °C
1
8
1
32
1
16
1
64
01234567
Figure 1. Temperature Measured in 1/64°C Steps
-50°C
00110111
TWO'S
COMPLEMENT
RESLO
RESHI
01234567
89101112131415
Figure 2. Conversion of Temperature Done in Two’s
Complement
BINARY
TEMP
(°C)
RELATIVE
TEMP (°C)
HEX
RESHI RESLO
+94 -1 FFC0h 1111 1111 1100 0000
+85 -10 FD80h 1111 1101 1000 0000
+70 -25 FDC0h 1111 1101 1100 0000
+45 -50 F380h 1111 0011 1000 0000
+20 -75 ED30h 1110 1101 0100 0000
Table 8. Example 16-Bit Representation
with No Offset (Activation Point = +95°C)
MAX6621
PECI-to-I
2
C Translator
_______________________________________________________________________________________ 9
Alternate Temperature Value Representation
This optional feature can be enabled using bit 6 of
CONFIG0. When the alternate data format is enabled, the
temperature value is shifted right as shown in Table 9.
The most significant bits are set to all 0s or all 1s depend-
ing on the sign bit 15, also shown as S in Figure 3. Table
10 shows some example values. This translation is not
performed for error codes (16-bit values from 8000h
through 81FFh).
Excluding error codes, the software only has to exam-
ine the RESLO data byte, as it represents an integer
value in the range from -128°C to +127°C in 1°C steps.
The RESHI byte is all 0s or all 1s for valid return codes,
and either 80h or 81h for all error codes.
Temperature Averaging
The MAX6621 can average several temperature read-
ings and return a value as calculated by:
where T
OLD
is the previously stored temperature, T
PECI
is the new value read from PECI, and T
NEW
is the newly
stored temperature ready to be returned through I
2
C.
This calculation can cause significant bits to be lost.
Enable temperature averaging by writing the desired
averaging amount to the CONFIG3 register. Writing 00h
to the CONFIG3 register disables temperature averaging.
TxT
NEW
CONFIG
PECI
CONFIG
=+
1
2
1
1
2
33
xT
OLD
S X X 12 11 10 9 8
7 6 X X X X X X
S S S S S S S S S 12 11 10 9 8 7 6
INTEGER VALUE (~ 1°C)(SIGN BITS)
RESHI
RESLO
FRACTIONAL VALUE
Figure 3. Alternate Temperature Representation
DESCRIPTION RESHI RESLO
16-bit value 15:14:13:12:11:10:9:8 7:6:5:4:3:2:1:0
Alternate
representation
15:15:15:15:15:15:15:15 15:12:11:10:9:8:7:6
Table 9. Alternate Temperature
Representation
BINARY
TEMP (°C) RELATIVE TEMP (°C) HEX
RESHI RESLO
+94 -1 FFFFh 1111 1111 1111 1111
+85 -10 FFF6h 1111 1111 1111 0110
+70 -25 FFE7h 1111 1111 1110 0111
+45 -50 FFCEh 1111 1111 1100 1110
+20 -75 FFB5h 1111 1111 1011 0101
Table 10. Example Alternate Representation with No Offset (Activation Point = +95°C)

MAX6621AUB+

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Maxim Integrated
Description:
Translation - Voltage Levels MAX6621 PROTOCOL CONVERTER USOP PB
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