7
Biasing and Operation
Recommended quiescent DC bias condition for optimum
power and linearity performances is Vdd=5 volts with Vgg
(-1V) set for Idq=700 mA. Minor improvements in perfor-
mance are possible depending on the application. The
drain bias voltage range is 3 to 5V. A single DC gate supply
connected to Vgg will bias all gain stages. Muting can be
accomplished by setting Vgg to the pinch-o voltage Vp
(-2V).
Figure 13. Schematic and recommended assemble example
RF_IN RF_OUT
Vdd
> 0.1 µF
8
1 2 3
4
567
100 pF
> 0.1 µF
100 pF> 0.1 µF
Note:
Vd3 may be biased
from either side.
Vgg
100 pF
Note: No RF performance degradation is seen due to ESD up to 250V HBM and 50V MM. The DC characteristics in general show increased leakage at
lower ESD discharge voltages. The user is reminded that this device is ESD sensitive and needs to be handled with all necessary ESD protocols.
A typical DC bias conguration is shown in Figure 13. Vd3
may be biased from either side (Pin 3 or Pin 5). The RF
input and output ports are DC decoupled internally. No
ground wires are needed since ground connections are
made with plated through-holes to the backside of the
device.
