10
Figure 4. Pre-Trigger Modes 0, 1, and 2.
Pre-Trigger Mode
The pre-trigger mode refers to the operation of a PLL-
based circuit that aects the sampling behavior and
conversion time of the A/D converter when channel 1
is selected. The PLL pre-trigger circuit has two modes of
operation; the rst mode allows more precise control of
the time at which the analog input voltage is eectively
sampled, while the second mode essentially eliminates
the time between when the external convert start
command is given and when output data is available
(reducing it to less than 1µs). A brief description of how
the A/D converter works with the pre-trigger circuit
disabled will help explain how the pre-trigger circuit
aects operation when it is enabled.
With the pre-trigger circuit is disabled (pre-trigger mode
0), Figure 4 illustrates the relationship between the
convert start command, the weighting function used to
average the modulator data, and the data ready signal.
The weighted averaging of the modulator data begins
immediately following the convert start command. The
weighting function increases for half of the conversion
cycle and then decreases back to zero, at which time the
data ready signal is given, completing the conversion
cycle. The analog signal is eectively sampled at the peak
of the weighting function, half-way through the conver-
sion cycle. This is the default mode.
If the convert start signal is periodic (i.e., at a xed
frequency) and the PLL pre-trigger circuit is enabled (pre-
trigger modes 1 or 2), either the peak of the weighting
function or the end of the conversion cycle can be
aligned to the external convert start command, as shown
in Figure 4. The Digital Interface IC can therefore synchro-
nize the conversion cycle so that either the beginning, the
middle, or the end of the conversion is aligned with the
external convert start command, depending on whether
pre-trigger mode 0, 1, or 2 is selected, respectively. The
only requirement is that the convert start signal for
channel 1 be periodic. If the signal is not periodic and
pre-trigger mode 1 or 2 is selected, then the pre-trigger
circuit will not function properly.
WEIGHTING
FUNCTION
CONVERT START - CS
DATA READY - SDAT
A) PRE-TRIGGER MODE 0 B) PRE-TRIGGER MODE 1 C) PRE-TRIGGER MODE 2
An important distinction should be made concerning the
dierence between conversion time and signal delay. As can
be seen in Figure 4, the amount of time from the peak of the
weighting function (when the input signal is being sampled)
to when output data is ready is the same for all three modes.
This is the actual delay of the analog signal through the
A/D converter and is independent of the “conversion time,”
which is simply the time between the convert start signal
and the data ready signal. Because signal delay is the true
measure of how much phase shift the A/D converter adds
to the signal, it should be used when making calculations of
phase margin and loop stability in feedback systems.
There are dierent reasons for using each of the pre-trigger
modes. If the signal is not periodic, then the pre-trigger
circuit should be disabled by selecting pre-trigger mode
0. If the most time-accurate sampling of the input signal
is desired, then mode 1 should be selected. If the shortest
possible conversion time is desired, then mode 2 should be
selected. The pre-trigger circuit functions only with channel
1; the circuit ignores any convert start signals while channel
2 is selected with the CHAN input. This allows conversions
on channel 2 to be performed between conversions on
channel 1 without aecting the operation of the pre-trigger
circuit. As long as the convert start signals are periodic
while channel 1 is selected, then the pre-trigger circuit will
function properly. The three dierent pre-trigger modes are
selected using bits 6 and 7 of register 3, as shown in Table
3 below.
Table 3. Pre-Trigger Mode Conguration.
Notes: Bold italic type indicates Default values.
Pre-Trigger
Mode
Conguration Data Bits
Bit 7 Bit 6
0 Low Low
1 Low High
2 High Don’t Care
Oset Calibration
The oset calibration circuit can be used to separately
calibrate the osets of both channels 1 and 2. The oset
calibration circuit contains a separate oset register for
each channel. After an oset calibration sequence, the
oset registers will contain a value equal to the measured
oset, which will then be subtracted from all subsequent
conversions. A hardware reset (bringing the RESET pin
high for at least 100 ns) is required to reset the oset
calibration registers to zero.
The following sequence is recommended for performing
an oset calibration:
1. Select the appropriate channel using the CHAN pin
(low = channel 1, high = channel 2).
2. Force zero volts at the input of the selected isolated
modulator.
3. Send a conguration data byte to the appropriate reg-
ister for the selected channel (register 0 for channel 1,
register 1 for channel 2). Bit 3 of the conguration byte
should be set high to enable oset calibration mode
and bits 4 through 7 should be set to select conversion
mode 1 to achieve the highest resolution measurement
of the oset.
4. Perform one complete conversion cycle by bringing
CS low until SDAT goes high, indicating completion of
the conversion cycle. Because bit 3 of the congura-
tion has been set high, the uncalibrated output data
from the conversion will be stored in the appropriate
oset calibration register and will be subtracted from
all subsequent conversions on that channel. If multiple
conversion cycles are performed while the oset cali-
bration mode is enabled, the uncalibrated data from
the last conversion cycle will be stored in the oset
calibration register.
5. Send another conguration byte to the appropriate
register for the selected channel, setting bit 3 low to
disable calibration mode and setting bits 4 through 7
to select the desired conversion mode for subsequent
conversions on that channel.
To calibrate both channels, perform the above sequence
for each channel. The oset calibration sequence can be
performed as often as needed. Table 4 below summarizes
how to turn the oset calibration mode on or o using
bit 3 of conguration registers 0 and 1.
Over-Range Detection
The over-range detection circuit allows fast detection
of when the magnitude of the input signal on channel
1 is near or beyond full-scale, causing the OVR1 output
to go high. This circuit can be very useful in current-
sensing applications for quickly detecting when a short-
circuit occurs. The over-range detection circuit works
by detecting when the modulator output data has not
changed state for at least 25 clock cycles in a row, indi-
cating that the input signal is near or beyond full-scale,
positive or negative. Typical response time to over-range
signals is less than 3µs.
The over-range circuit actually begins to indicate an over-
range condition when the magnitude of the input signal
exceeds approximately 250 mV; it starts to generate
periodic short pulses on OVR1, which get longer and
more frequent as the input signal approaches full scale.
The OVR1 output stays high continuously when the input
is beyond full-scale.
The over-range detection circuit continuously monitors
channel 1 independent of which channel is selected with
the CHAN signal. This allows continuous monitoring of
channel 1 for faults while converting an input signal on
channel 2.
Table 4. Oset Calibration Conguration.
Notes: Bold italic type indicates Default values.
Oset Calibration
Mode
Conguration Data Bits
Bit 3
O Low
On High
12
Adjustable Threshold Detection
The adjustable threshold detector causes the THR1 output
to go high when the magnitude of the input signal on
channel 1 exceeds a user-dened threshold level. The
threshold level can be set to one of 16 dierent values
between approximately 160 mV and 310 mV. The adjust-
able threshold detector uses a smaller version of the main
conversion circuit in combination with a digital compara-
tor to detect when the magnitude of the input signal on
channel 1 is beyond the dened threshold level. As with
the main conversion circuit, there is a trade-o between
speed and resolution with the threshold detector;
selecting faster detection times exhibit more noise as
the signal passes through the threshold, while slower
detection times oer lower noise. Both the detection
time and threshold level are programmable using bits 2
through 7 of conguration register 2, as shown in Tables
5 and 6 below.
As with the over-range detector, the adjustable threshold
detector continuously monitors channel 1 independent
of which channel is selected with the CHAN signal. This
allows continuous monitoring of channel 1 for faults
while converting Channel 2.
Table 6. Threshold Level Conguration.
Table 5. Threshold Detection Conguration.
Notes: Bold italic type indicates Default values.
Notes: Bold italic type indicates Default values.
Threshold
Detection
Time
Conguration Data Bits
Bit 7 Bit 6
2 - 6 µs Low Low
3 - 10 µs Low High
5 - 20 µs High Low
10 - 35 µs High High
Threshold
Level
Conguration Data Bits
Bit 5 Bit 4 Bit 3 Bit 2
±160 mV Low Low Low Low
± 170 mV
Low
Low
Low High
± 180 mV
High
Low
± 190 mV High
± 200 mV
High
Low
Low
± 210 mV High
± 220 mV
High
Low
± 230 mV High
± 240 mV
High
Low
Low
Low
± 250 mV High
± 260 mV
High
Low
± 270 mV High
± 280 mV
High
Low
Low
± 290 mV High
± 300 mV
High
Low
± 310 mV High
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2165EN
AV02-0411EN - May 14, 2007

HCPL-0872

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Interface - Specialized Digital Interface IC
Lifecycle:
New from this manufacturer.
Delivery:
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