7
Digital Interface Timing
Power Up/Reset
At power up, the digital interface IC should be reset
either manually, by bringing the RESET pin (pin 9) high
for at least 100 ns, or automatically by connecting a
10µF capacitor between the RESET pin and V
DD
(pin 16).
The RESET pin operates asynchronously and places the
IC in its default conguration, as specied in the Digital
Interface Conguration section.
Figure 2. Conversion Timing.
Conversion Timing
Figure 2 illustrates the timing for one complete conver-
sion cycle. A conversion cycle is initiated on the falling
edge of the convert start signal (CS); CS should be held
low during the entire conversion cycle. When CS is
brought low, the serial output data line (SDAT) changes
from a high-impedance to the low state, indicating that
the converter is busy. A rising edge on SDAT indicates
that data is ready to be clocked out. The output data
is clocked out on the negative edges of the serial clock
pulses (SCLK), MSB rst. A total of 16 pulses is needed
to clock out all of the data. After the last clock pulse, CS
should be brought high again, causing SDAT to return to
a high-impedance state, completing the conversion cycle.
If the external circuit uses the positive edges of SCLK to
clock in the data, then a total of sixteen bits is clocked in,
the rst bit is always high (indicating that data is ready)
followed by 15 data bits. If fewer than 16 cycles of SCLK
are input before CS is brought high, the conversion cycle
will terminate and SDAT will go to the high-impedance
state after a few cycles of the Isolated Modulator’s clock.
The amount of time between the falling edge of CS and
the rising edge of SDAT depends on which conversion
and pre-trigger modes are selected; it can be as low as
0.7µs when using pre-trigger mode 2, as explained in the
Digital Interface Conguration section.
SCLK
SDAT
CHAN
t
SUCHS
t
DSDAT
t
C
t
SUS
B14 B13 B12 B11 B10 B1 B0
1 2 3 4 5 6
t
PER
t
PWL
15 16
t
PWH
CS
