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74LV86PW,112
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P16
74L
V86_3
© NXP B.V
. 2007. All rights reserved.
Product data sheet
Rev
. 03 — 27 November 2007
9 of 15
NXP Semiconductors
74L
V86
Quad 2-input exc
lusive-OR gate
Fig 9.
P
ackage outline SO
T108-1 (SO14)
UNIT
A
max.
A
1
A
2
A
3
b
p
cD
(1)
E
(1)
(1)
eH
E
LL
p
QZ
y
w
v
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25
0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
w
M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
7
8
1
14
y
076E06
MS-012
pin 1 index
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.35
0.34
0.16
0.15
0.05
1.05
0.041
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.25
0.01
0.004
0.039
0.016
99-12-27
03-02-19
0
2.5
5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
74L
V86_3
© NXP B.V
. 2007. All rights reserved.
Product data sheet
Rev
. 03 — 27 November 2007
10 of 15
NXP Semiconductors
74L
V86
Quad 2-input exc
lusive-OR gate
Fig 10.
P
ackage outline SO
T337-1 (SSOP14)
UNIT
A
1
A
2
A
3
b
p
cD
(1)
E
(1)
eH
E
LL
p
QZ
y
w
v
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
1.25
0.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
8
0
o
o
0.13
0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1
99-12-27
03-02-19
(1)
w
M
b
p
D
H
E
E
Z
e
c
v
M
A
X
A
y
1
7
14
8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150
pin 1 index
0
2.5
5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
A
max.
2
74L
V86_3
© NXP B.V
. 2007. All rights reserved.
Product data sheet
Rev
. 03 — 27 November 2007
11 of 15
NXP Semiconductors
74L
V86
Quad 2-input exc
lusive-OR gate
Fig 11.
P
ackage outline SO
T402-1 (TSSOP14)
UNIT
A
1
A
2
A
3
b
p
cD
(1)
E
(2)
(1)
eH
E
LL
p
QZ
y
w
v
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.72
0.38
8
0
o
o
0.13
0.1
0.2
1
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1
MO-153
99-12-27
03-02-18
w
M
b
p
D
Z
e
0.25
17
14
8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v
M
A
X
A
y
0
2.5
5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
A
max.
1.1
pin 1 index
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P16
74LV86PW,112
Mfr. #:
Buy 74LV86PW,112
Manufacturer:
NXP Semiconductors
Description:
IC GATE XOR 4CH 2-INP 14TSSOP
Lifecycle:
New from this manufacturer.
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