74LV86_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 27 November 2007 6 of 15
NXP Semiconductors
74LV86
Quad 2-input exclusive-OR gate
10. Dynamic characteristics
[1] All typical values are measured at T
amb
=25°C.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] Typical values are measured at nominal supply voltage (V
CC
= 3.3 V).
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz, f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
N = number of inputs switching
Σ(C
L
× V
CC
2
× f
o
) = sum of the outputs.
Table 7. Dynamic characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter Conditions 40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation delay nA, nB to nY; see Figure 6
[2]
V
CC
= 1.2 V - 70 - - - ns
V
CC
= 2.0 V - 24 32 - 41 ns
V
CC
= 2.7 V - 18 24 - 30 ns
V
CC
= 3.0 V to 3.6 V; C
L
=15pF
[3]
-11- - -ns
V
CC
= 3.0 V to 3.6 V
[3]
- 13 19 - 24 ns
V
CC
= 4.5 V to 5.5 V - - 16 - 20 ns
C
PD
power dissipation
capacitance
C
L
= 50 pF; f
i
= 1 MHz;
V
I
= GND to V
CC
[4]
-30- - -pF
74LV86_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 27 November 2007 7 of 15
NXP Semiconductors
74LV86
Quad 2-input exclusive-OR gate
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. The input (nA, nB) to output (nY) propagation delays
mna224
nA, nB input
nY output
t
PLH
t
PHL
GND
V
I
V
M
V
M
V
OH
V
OL
Table 8. Measurement points
Supply voltage
V
CC
Input
V
M
Output
V
M
< 2.7 V 0.5V
CC
0.5V
CC
2.7 V to 3.6 V 1.5 V 1.5 V
4.5 V 0.5V
CC
0.5V
CC
Test data is given in Table 9.
Definitions test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
Fig 7. Load circuit for switching times
V
CC
V
I
V
O
001aaa663
D.U.T.
C
L
50 pF
R
T
R
L
1 k
PULSE
GENERATOR
Table 9. Test data
Supply voltage
V
CC
Input
V
I
t
r
, t
f
< 2.7 V V
CC
2.5 ns
2.7 V to 3.6 V 2.7 V 2.5 ns
4.5 V V
CC
2.5 ns
74LV86_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 27 November 2007 8 of 15
NXP Semiconductors
74LV86
Quad 2-input exclusive-OR gate
12. Package outline
Fig 8. Package outline SOT27-1 (DIP14)
UNIT
A
max.
1 2
(1) (1)
b
1
cD
(1)
Z
Ee M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1
99-12-27
03-02-13
A
min.
A
max.
b
max.
w
M
E
e
1
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
0.2542.54 7.62
8.25
7.80
10.0
8.3
2.24.2 0.51 3.2
0.068
0.044
0.021
0.015
0.77
0.73
0.014
0.009
0.26
0.24
0.14
0.12
0.010.1 0.3
0.32
0.31
0.39
0.33
0.0870.17 0.02 0.13
050G04 MO-001 SC-501-14
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w M
b
1
e
D
A
2
Z
14
1
8
7
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1

74LV86PW,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC GATE XOR 4CH 2-INP 14TSSOP
Lifecycle:
New from this manufacturer.
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