MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
_______________________________________________________________________________________ 5
ns100t
CSS
Figure 1, external clock mode only,
C
LOAD
= 100pF
ns
CS to SCLK Rise Setup
240
Figure 1, C
LOAD
= 100pF ns
20 200
ns0t
CSH
CONDITIONS
CS to SCLK Rise Hold
240
t
DV
CS Fall to Output Enable
Figure 2, C
LOAD
= 100pF ns240t
TR
CS Rise to Output Disable
t
SDV
CS Fall to SSTRB Output Enable
(Note 5)
Figure 2, external clock mode only,
C
LOAD
= 100pF
ns240t
STR
CS Rise to SSTRB Output
Disable (Note 5)
Figure 11, internal clock mode only ns0t
SCK
SSTRB Rise to SCLK Rise
(Note 5)
ns200t
CH
SCLK Pulse Width High
ns200t
CL
SCLK Pulse Width Low
C
LOAD
= 100pF ns240t
SSTRB
SCLK Fall to SSTRB
ns0t
DH
DIN to SCLK Hold
µs1t
ACQ
Track/Hold Acquisition Time
ns100t
DS
DIN to SCLK Setup
UNITSMIN TYP MAXSYMBOLPARAMETER
TIMING CHARACTERISTICS (Figures 8 and 9)
(V
DD
= 4.5V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2: V
REFIN
= 4.096V, offset nulled.
Note 3: On-channel grounded; sine wave applied to all off-channels.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: Common-mode range for the analog inputs is from AGND to V
DD
.
Note 7: External load should not change during the conversion for specified accuracy.
Note 8: External reference at 4.096V, full-scale input, 500kHz external clock.
Note 9: Measured as
| V
FS
(4.5V) - V
FS
(5.5V) |.
Note 10: 1µF at REFOUT; internal reference settling to 0.5 LSB.
nst
DO
SCLK Fall to Output Data Valid Figure 1, C
LOAD
= 100pF
External reference 20
Internal reference (Note 10)
µs
24
t
WAKE
Wakeup Time
ms
