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CY2CC810OXCT

P1-P3P4-P6P7-P9
1:10 Clock Fanout Buffe
r
CY2CC810
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07056 Rev. *E Revised September 5, 2006
Features
• Low-voltage operation
•V
DD
range from 2.5V to 3.3V
• 1:10 fanout
• Over voltage tolerant input hot swappable
• Drives either a 50-Ohm or 75-Ohm transmission line
• Low-input capacitance
• 250 ps typical output-to-output skew
• 19 ps typical DJ jitter
• Typical propagation delay < 3.5 ns
• High-speed operation > 500 MHz
• Industrial versions available
• Available packages include: SOIC, SSOP
Description
The Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic and buffers.
The Cypress CY2CC810 fanout buffer features one input and
ten outputs. Designed for data communications clock
management applications, the large fanout from a single input
reduces loading on the input clock.
AVCMOS-type outputs dynamically adjust for variable
impedance matching and reduce noise overall.
.
Block Diagram Pin Configuration
OUTPUT
(AVCMOS)
IN
Q1
Q5
Q7
Q6
Q4
Q3
Q2
Q8
Q9
Q10
GND
VDD
INPUT
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
CY2CC810
20 pin SOIC/SSOP
VDD
Q10
Q9
GND
Q8
VDD
Q7
GND
Q6
Q5
IN
GND
Q1
VDD
Q2
GND
Q3
VDD
Q4
GND
Pin Description
Pin Number Pin Name Description
1 IN Input LVCMOS
2, 6, 10, 13, 17 GND Ground Power
4, 8, 15, 20
V
DD
Power Supply Power
3, 5, 7, 9, 11, 12, 14, 16, 18, 19 Q1... Q10 Output AVCMOS
[+] Feedback
CY2CC810
Document #: 38-07056 Rev. *E Page 2 of 9
Absolute Maximum Conditions
[1, 2]
Parameter Description Min. Max. Unit
V
DD
V
DD
Ground Supply voltage –0.5 4.6 V
V
IN
Input Supply Voltage to Ground Potential –0.5 5.8 V
V
OUT
Output Supply Voltage to Ground Potential –0.5 V
DD
+1 V
T
S
Temperature, Storage –65 150 °C
T
A
Temperature, Operating Ambient –40 85 °C
Power Dissipation 0.75 W
DC Electrical Characteristics @ 3.3V (see Figure 5)
Parameter Description Conditions Min. Typ. Max. Unit
V
OH
Output High Voltage V
DD
= Min., V
IN
= V
IH
or V
IL
I
OH
= –12 mA 2.3 3.3 V
V
OL
Output Low Voltage V
DD
= Min., V
IN
= V
IH
or V
IL
I
OL
= 12 mA 0.2 0.5 V
V
IH
Input High Voltage Guaranteed Logic High Level 2 5.8 V
V
IL
Input Low Voltage Guaranteed Logic Low Level 0.8 V
I
IH
Input High Current V
DD
= Max. V
IN
= 2.7V 1 µA
I
IL
Input Low Current V
DD
= Max. V
IN
= 0.5V –1 µA
I
I
Input High Current V
DD
= Max., V
IN
= V
DD
(Max.) 20 µA
V
IK
Clamp Diode Voltage V
DD
= Min., I
IN
= –18 mA –0.7 –1.2 V
I
OK
Continuous Clamp Current V
DD
= Max., V
OUT
= GND –50 mA
O
OFF
Power down Disable V
DD
= GND, V
OUT
= < 4.5V 100 µA
V
H
Input Hysteresis V
DD
= Min., V
IN
= V
IH
or V
IL
80 mV
DC Electrical Characteristics @ 2.5V (see Figure 1)
Parameter Description Conditions Min. Typ. Max. Unit
V
OH
Output High Voltage V
DD
= Min., V
IN
= V
IH
or V
IL
I
OH
= –7 mA 1.8 V
I
OH
= 12 mA 1.6 V
V
OL
Output Low Voltage V
DD
= Min., V
IN
= V
IH
or V
IL
I
OL
= 12 mA 0.65 V
V
IH
Input High Voltage Guaranteed Logic High Level 1.6 5.0 V
V
IL
Input Low Voltage Guaranteed Logic Low Level 0.8 V
I
IH
Input High Current V
DD
= Max. V
IN
= 2.4V 1 µA
I
IL
Input Low Current V
DD
= Max. V
IN
= 0.5V –1 µA
I
I
Input High Current V
DD
= Max., V
IN
= V
DD
(Max.) 20 µA
V
IK
Clamp Diode Voltage V
DD
= Min., I
IN
= –18 mA –0.7 –1.2 V
I
OK
Continuous Clamp Current V
DD
= Max., V
OUT
= GND –50 mA
O
OFF
Power-down Disable V
DD
= GND, V
OUT
= < 4.5V 100 µA
V
H
Input Hysteresis 80 mV
Note
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Capacitance
Parameter Description Test Conditions Min. Typ. Max. Unit
Cin Input Capacitance V
IN
= 0V
2.5 pF
Cout Output Capacitance V
OUT
= 0V
6.5 pF
[+] Feedback
CY2CC810
Document #: 38-07056 Rev. *E Page 3 of 9
Power Supply Characteristics (see Figure 5)
Parameter Description Test Conditions Min. Typ. Max. Unit
∆
ICC
Delta I
CC
Quiescent Power
Supply Current
(I
DD
@ V
DD
= Max. and V
IN
= V
DD
) – (I
DD
@ V
DD
= Max.
and V
IN
= V
DD
– 0.6V)
50 µA
I
CCD
Dynamic Power Supply
Current
V
DD
= Max.
Input toggling 50% Duty Cycle, Outputs Open
0.63 mA/
MHz
I
C
Total Power Supply Current V
DD
= Max.
Input toggling 50% Duty Cycle, Outputs Open
fL = 40 MHZ
25 mA
t
PU
Power-up time for all V
DD
s Power-up to reach minimum specified voltage
(power ramp must be monotonic)
0.05 500 ms
High-frequency Parametrics
Parameter Description Test Conditions Min. Typ. Max. Unit
D
J
Jitter, Deterministic 50% duty cycle t
W
(50–50)
The “point to point load circuit”
Output Jitter – Input Jitter
2.5V 23 35 ps
3.3V 19 30 ps
F
max(3.3V)
Maximum frequency
V
DD
= 3.3V
50% duty cycle t
W
(50–50)
Standard Load Circuit.
See Figure 5 160 MHz
50% duty cycle t
W
(50–50)
The “point to point load circuit”
See Figure 7 650
F
max(2.5V
Maximum frequency
V
DD
= 2.5 V
The “point to point load circuit”
V
IN
= 2.4V/0.0V V
OUT
= 1.7V/0.7V
See Figure 7 200 MHz
F
max(20)
Maximum frequency
V
DD
= 3.3 V
20% duty cycle t
W
(20–80)
The “point to point load circuit”
V
IN
= 3.0V/0.0V V
OUT
= 2.3V/0.4V
See Figure 7 250 MHz
Maximum frequency
V
DD
= 2.5 V
The “point to point load circuit”
V
IN
= 2.4V/0.0V V
OUT
= 1.7V/0.7V
See Figure 3 200 MHz
t
W
Minimum pulse
V
DD
= 3.3 V
The “point to point load circuit”
V
IN
= 3.0V/0.0V F = 100 MHz
V
OUT
= 2.0V/0.8V
See Figure 7 1ns
Minimum pulse
V
DD
= 2.5 V
The “point to point load circuit”
V
IN
= 2.4V/0.0V F = 100 MHz
V
OUT
= 1.7V/0.7V
See Figure 3 1
AC Switching Characteristics @ 3.3V, V
DD
= 3.3V ±5%, Temperature = –40°C to +85°C
Parameter Description Min. Typ. Max. Unit
t
PLH
Propagation Delay – Low to High See Figure 4 1.5 2.7 3.5 ns
t
PHL
Propagation Delay – High to Low 1.5 2.7 3.5 ns
t
R
Output Rise Time 0.8 V/ns
t
F
Output Fall Time 0.8 V/ns
t
SK(0)
Output Skew: Skew between outputs of the same package (in phase) See Figure 10 0.25 0.38 ns
t
SK(p)
Pulse Skew: Skew between opposite transitions of the same output
(t
PHL
– t
PLH
).
See Figure 9 0.2 ns
t
SK(t)
Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type.
See Figure 11 0.42 ns
[+] Feedback
P1-P3P4-P6P7-P9

CY2CC810OXCT

Mfr. #:
Buy CY2CC810OXCT
Manufacturer:
Cypress Semiconductor
Description:
IC CLK BUFFER 1:10 650MHZ 20SSOP
Lifecycle:
New from this manufacturer.
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