ADG5419 Data Sheet
Rev. A | Page 18 of 19
APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, aerospace, and
other harsh environments that are prone to latch-up, which is an
undesirable high current state that can lead to device failure and
persists until the power supply is turned off. The ADG5419
high voltage switch allows single-supply operation from 9 V
to 40 V and dual-supply operation from ±9 V to ±22 V. The
ADG5419 (as well as other select devices within this family)
achieves an 8 kV human body model ESD rating, which provides
a robust solution, eliminating the need for separate protection
circuitry designs in some applications.
TRENCH ISOLATION
In the ADG5419, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction-isolated switches, are eliminated, and the result is a
completely latch-up immune switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. The two transistors form a
silicon-controlled rectifier (SCR) type circuit, causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up immune switch.
Figure 36. Trench Isolation
11370-030
NMOS PMOS
P-WELL N-WELL
BURIED OXIDE LAYER
HANDLE WAFER
TRENCH
