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CAT93C66LI-G

P1-P3P4-P6P7-P9P10-P12P13-P13
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 13
1 Publication Order Number:
CAT93C66/D
CAT93C66, CAT93W66
4 kb Microwire Serial CMOS
EEPROM
Description
The CAT93C66 is a 4 kb CMOS Serial EEPROM device which is
organized as either 256 registers of 16 bits (ORG pin at V
CC
) or 512
registers of 8 bits (ORG pin at GND). The CAT93W66 features x16
memory organization only. Each register can be written (or read)
serially by using the DI (or DO) pin. The device features sequential
read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
Features
• High Speed Operation: 2 MHz
• 1.8 V to 5.5 V Supply Voltage Range
• Selectable x8 or x16 Memory Organization: CAT93C66
• Sequential Read
• Software Write Protection
• Power−up Inadvertent Write Protection
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Ranges
• 8−lead PDIP, SOIC, TSSOP and 8−pad TDFN Packages
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
ORG
DO
CAT93C66
SK
GND
V
CC
Figure 1. Functional Symbols
DI
CS
DO
CAT93W66
SK
GND
V
CC
DI
CS
CAT93C66 Selectable Organization:
When the ORG pin is connected to V
CC
, the x16 organization is
selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pull−up
device will select the x16 organization.
CAT93W66*:
The device works in x16 mode only.
*Not recommended for new designs
www.onsemi.com
PIN CONFIGURATION
(Top View)
DO
DI
SK
CS
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
ORDERING INFORMATION
SOIC−8
V SUFFIX
CASE 751BD
TDFN−8
VP2 SUFFIX
CASE 511AK
PDIP (L), SOIC (V, X),
TSSOP (Y),
TDFN (VP2)
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
X SUFFIX
CASE 751BE
GND
ORG
NC
V
CC
1
2
3
4
8
7
6
5
TDFN (VP2)
CAT93W66*
DO
DI
SK
CS
GND
NC
NC
V
CC
1
2
3
4
8
7
6
5
CAT93C66, CAT93W66
www.onsemi.com
2
Table 1. PIN FUNCTION
Pin Name Function Pin Name Function
CS Chip Select V
CC
Power Supply
SK Clock Input GND Ground
DI Serial Data Input ORG (Note 1) Memory Organization
DO Serial Data Output NC No Connection
1. ORG Pin available for the CAT93C66 only.
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Storage Temperature −65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 2) −0.5 to +6.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. The DC input voltage on any pin should not be lower than −0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 3. RELIABILITY CHARACTERISTICS (Note 3)
Symbol Parameter Min Units
N
END
(Note 4) Endurance 1,000,000 Program / Erase Cycles
T
DR
Data Retention 100 Years
3. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
4. Block Mode, V
CC
= 5 V, 25°C.
Table 4. D.C. OPERATING CHARACTERISTICS
(V
CC
= +1.8 V to +5.5 V, T
A
= −40°C to +125°C unless otherwise specified.)
Symbol
Parameter Test Conditions Min Max Units
I
CC1
Power Supply Current
(Write)
f
SK
= 1 MHz, V
CC
= 5.0 V 1 mA
I
CC2
Power Supply Current
(Read)
f
SK
= 1 MHz, V
CC
= 5.0 V 500
mA
I
SB1
Power Supply Current
(Standby) (x8 Mode)
V
IN
= GND or V
CC
,
CS = GND ORG = GND
T
A
= −40°C to +85°C 2 mA
T
A
= −40°C to +125°C 4
I
SB2
Power Supply Current
(Standby) (x16 Mode)
V
IN
= GND or V
CC
, CS = GND
ORG = Float or V
CC
T
A
= −40°C to +85°C 1 mA
T
A
= −40°C to +125°C 2
I
LI
Input Leakage Current V
IN
= GND to V
CC
T
A
= −40°C to +85°C 1 mA
T
A
= −40°C to +125°C 2
I
LO
Output Leakage Current V
OUT
= GND to V
CC
,
CS = GND
T
A
= −40°C to +85°C 1 mA
T
A
= −40°C to +125°C 2
V
IL1
Input Low Voltage 4.5 V ≤ V
CC
< 5.5 V −0.1 0.8 V
V
IH1
Input High Voltage 4.5 V ≤ V
CC
< 5.5 V 2 V
CC
+ 1 V
V
IL2
Input Low Voltage 1.8 V ≤ V
CC
< 4.5 V 0 V
CC
x 0.2 V
V
IH2
Input High Voltage 1.8 V ≤ V
CC
< 4.5 V V
CC
x 0.7 V
CC
+ 1 V
V
OL1
Output Low Voltage 4.5 V ≤ V
CC
< 5.5 V, I
OL
= 2.1 mA 0.4 V
V
OH1
Output High Voltage
4.5 V ≤ V
CC
< 5.5 V, I
OH
= −400 mA
2.4 V
V
OL2
Output Low Voltage 1.8 V ≤ V
CC
< 4.5 V, I
OL
= 1 mA 0.2 V
V
OH2
Output High Voltage
1.8 V ≤ V
CC
< 4.5 V, I
OH
= −100 mA
V
CC
− 0.2 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
CAT93C66, CAT93W66
www.onsemi.com
3
Table 5. PIN CAPACITANCE (T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V)
Symbol
Test Conditions Min Typ Max Units
C
OUT
(Note 5) Output Capacitance (DO) V
OUT
= 0 V 5 pF
C
IN
(Note 5) Input Capacitance (CS, SK, DI, ORG) V
IN
= 0 V 5 pF
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 6. A.C. CHARACTERISTICS
(V
CC
= +1.8 V to +5.5 V, T
A
= −40°C to +125°C, unless otherwise specified.) (Note 6)
Symbol
Parameter
Limits
Units
Min Max
t
CSS
CS Setup Time 50 ns
t
CSH
CS Hold Time 0 ns
t
DIS
DI Setup Time 100 ns
t
DIH
DI Hold Time 100 ns
t
PD1
Output Delay to 1 0.25
ms
t
PD0
Output Delay to 0 0.25
ms
t
HZ
(Note 7) Output Delay to High−Z 100 ns
t
EW
Program/Erase Pulse Width 5 ms
t
CSMIN
Minimum CS Low Time 0.25
ms
t
SKHI
Minimum SK High Time 0.25
ms
t
SKLOW
Minimum SK Low Time 0.25
ms
t
SV
Output Delay to Status Valid 0.25
ms
SK
MAX
Maximum Clock Frequency DC 2000 kHz
6. Test conditions according to “A.C. Test Conditions” table.
7. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
Table 7. POWER−UP TIMING (Notes 8, 9)
Symbol
Parameter Max Units
t
PUR
Power−up to Read Operation 1 ms
t
PUW
Power−up to Write Operation 1 ms
8. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
9. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
P1-P3P4-P6P7-P9P10-P12P13-P13

CAT93C66LI-G

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