830S21AMILFT

1©2015 Integrated Device Technology, Inc December 10, 2015
CLK
nCLK
V
BB
Q
Pullup/Pulldown
Pullup/Pulldown
1
2
3
4
8
7
6
5
nc
CLK
nCLK
V
BB
VDD
Q
nc
GND
General Description
830s21I is a 1-to-1 Differential-to- LVCMOS/ LVTTL translator and
a member of the family of High Performance Clock Solutions from
IDT. The differential input is highly flexible and can accept the
following input types: LVPECL, LVDS, LVHSTL, SSTL and HCSL.
The small 8-lead SOIC footprint makes this device ideal for use in
applications with limited board space.
Features
One LVCMOS/LVTTL output
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 350MHz
Part-to-part skew: 525ps (maximum)
Additive Phase jitter, RMS: 0.11ps (typical)
Small 8 lead SOIC package saves board space
Full 3.3V and 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
830s21I
8-Lead SOIC
3.9mm x 4.9mm x 1.375mm package body
M Package
Top View
Pin Assignment
Block Diagram
830S21I
Datasheet
1-to-1 2.5V, 3.3V
Differential-to-LVCMOS/LVTTL Translator
2©2015 Integrated Device Technology, Inc December 10, 2015
830S21I Datasheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 6 nc Unused No connect.
2 CLK Input
Pullup/
Pulldown
Non-inverting differential clock input.
3 nCLK Input
Pullup/
Pulldown
Inverting differential clock input.
4V
BB
Output Output reference voltage.
5 GND Power Power supply ground.
7 Q Output Single-ended clock output. LVCMOS / LVTTL interface levels.
8V
DD
Power Positive supply pin.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
C
PD
Power Dissipation Capacitance
V
DD
= 3.465V 10 pF
V
DD
= 2.625V 8 pF
R
OUT
Output Impedance
V
DD
= 3.3V 10
V
DD
= 2.5V 12
3©2015 Integrated Device Technology, Inc December 10, 2015
830S21I Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Table 3B. Power Supply DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Table 3C. LVCMOS/LVTTL DC Characteristics, V
DD
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE 1: Outputs terminated with 50 to V
DD
/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
93.1C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 12 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 11 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1
V
DD
= 3.3V 2.6 V
V
DD
= 2.5V 1.8 V
V
OL
Output Low Voltage; NOTE 1 V
DD
= 3.3V or 2.5V 0.5 V

830S21AMILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 1 OUT DIFF TO LVTTL BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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