830S21AMILFT

4©2015 Integrated Device Technology, Inc December 10, 2015
830S21I Datasheet
Table 3D. Differential DC Characteristics, V
DD
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE 1:V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
AC Electrical Characteristics
Table 4A. AC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE 1: Measured from the differential input crossing point to the output at V
DD
/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V
DD
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Table 4B. AC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE 1: Measured from the differential input crossing point to the output at V
DD
/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V
DD
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current V
DD
= V
IN
= 3.465V or 2.625V 150 µA
I
IL
Input Low Current V
DD
= 3.465V or 2.625V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Voltage; NOTE 1 0.15 1.5 V
V
CMR
Common Mode Input Voltage;
NOTE 1, 2
GND + 0.5 V
DD
– 0.85 V
V
BB
Output Voltage Reference V
DD
– 1.4 V
DD
– 1.3 V
DD
– 1.2 V
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
t
PD
Propagation Delay, NOTE 1 0.95 1.95 ns
tsk(pp) Part-to-Part Skew; NOTE 2, 3 525 ps
tjit
Buffer Additive Phase jitter, RMS;
refer to Additive Phase Jitter Section
350MHz, Integration Range
(12kHz – 20MHz)
0.11 1 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 85 500 ps
odc Output Duty Cycle ƒ 266MHz 47 53 %
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
t
PD
Propagation Delay, NOTE 1 1 2 ns
tsk(pp) Part-to-Part Skew; NOTE 2, 3 550 ps
tjit
Buffer Additive Phase jitter, RMS;
refer to Additive Phase Jitter Section
350MHz, Integration Range
(12kHz – 20MHz)
0.11 1 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 125 500 ps
odc Output Duty Cycle ƒ 266MHz 47 53 %
5©2015 Integrated Device Technology, Inc December 10, 2015
830S21I Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what
is shown, but can actually be lower. The phase noise is dependent
on the input source and measurement equipment.
SSB Phase Noise dBc/Hz
Offset Frequency (Hz)
Additive Phase Jitter @ 350MHz
12kHz to 20MHz = 0.11ps (typical)
6©2015 Integrated Device Technology, Inc December 10, 2015
830S21I Datasheet
Parameter Measurement Information
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
Differential Input Level
Output Duty Cycle/Pulse Width/Period
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
Propagation Delay
Output Rise/Fall Time
SCOPE
Qx
GND
V
DD
1.65V±5%
-1.65V±5%
V
DD
GND
V
CMR
Cross Points
V
PP
CLK
nCLK
Q
SCOPE
Qx
GND
V
DD
1.25V±5%
-1.25V±5%
t
PD
V
DD
2
Q
CLK
nCLK
20%
80%
80%
20%
t
R
t
F
Q

830S21AMILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 1 OUT DIFF TO LVTTL BUFFER
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