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CSIX-LEV1-O4-N1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
Lattice Semiconductor CSIX Level 1 IP Core User’s Guide
13
Detailed Register Descriptions (Continued)
Address:
0x8148
Name:
Parity Error Register
D7
D6 D5 D4 D3 D2 D1 D0
VPERR_3 VPERR_2 VPERR_1 VPERR_0 HPERR_3 HPERR_2 HPERR_1 HPERR_0
Default value: n/a Mode: Clear on Read
Description:
HPERR_N When high, indicates that a horizontal parity error occurred on the inbound CSIX port for chan-
nel N. This bit clears upon reading. If the stimulus that caused the error is removed, then the
error bit in this register will clear after reading.
VPERR_N When high, indicates that a vertical parity error occurred on the inbound CSIX port for channel
N. This bit clears upon reading. If the stimulus that caused the error is removed, then the error
bit in this register will clear after reading.
Address:
0x814C
Name:
Miscellaneous Error Register
D7
D6 D5 D4 D3 D2 D1 D0
— — — — — — SYNC_ERR_1 SYNC_ERR_0
Default value: n/a Mode: Clear on Read
Description:
SYNC_ERR_0 This bit operates only when port aggregation is instantiated. When high, indicates that the
channels associated with aggregation span 0 experienced a sync error on the inbound CSIX
ports. This bit clears upon reading. If the stimulus that caused the error is removed, then the
error bit in this register will clear after reading.
SYNC_ERR_1 This bit operates only when aggregation span 1 is instantiated. When high, indicates that the
channels associated with aggregation span 1 experienced a sync error on the inbound CSIX
ports. This bit clears upon reading. If the stimulus that caused the error is removed, then the
error bit in this register will clear after reading.
Lattice Semiconductor CSIX Level 1 IP Core User’s Guide
14
Interface Timing and Electrical Specifications
CSIX Ports
The core’s CSIX ports are characterized to operate at 100MHz. Incoming signals are sampled on the rising edge of
the CSIX input clock. Outgoing signals are clocked on the rising edge of the outgoing CSIX clock. The instantiated
I/O buffers for the CSIX ports are compatible with LVCMOS and HSTL levels. Detailed timing and electrical specifi-
cations are shown in the paragraphs below.
The following figure shows a 64-byte payload arriving at the inbound CSIX interface. Note that the frame is actually
72 bytes long with header and vertical parity added.
Figure 2. CSIX Inbound Frame Transfer
The AC timing specifications for the inbound CSIX port are as follows:
Figure 3. CSIX Inbound AC Timing Specifications
The DC electrical specifications for the inbound CSIX port are as follows:
The following figure shows a 64-byte payload leaving the outbound CSIX interface. Note that the frame is actually
72 bytes long with header and vertical parity added.
Name Description Min. Max.
tclk_freq
Clock frequency — 100MHz
tclk_period Clock period 10ns —
t_setup Setup time to rising edge of clock 1.5ns —
t_hold Hold time to rising edge of clock 0ns —
Name
Description Min. Typ. Max.
V
DDIO
I/O supply voltage
2.3V 2.5V 2.7V
V
IH
V
IN
high threshold
2.0V — V
DDIO
+ 0.3V
V
IL
V
IN
low threshold
-0.5V — 0.8V
c6_clk_in_N_ext
c6_sof_in_N_ext
c6_parity_in_N_ext
c6_data_in_N_ext[31:0]
1
,
2
,
3 5,6,7
65,66,
67,68
69,70,
71,72
c6_clk_in_N_ext
c6_signal_in_N_ext
tclk_period
t_setup
t_hold
Lattice Semiconductor CSIX Level 1 IP Core User’s Guide
15
Figure 4. CSIX Outbound Frame Transfer
The AC timing specifications for the outbound CSIX port are as follows:
Figure 5. CSIX Outbound AC Timing Specifications
The DC electrical specifications for the inbound CSIX port are as follows:
Generic FIFO Bridge Ports
The Generic FIFO Bridge interface is buried inside the FPGA. No I/O buffers are allocated to any signals of the
Generic FIFO Bridge interface. Timing specifications are tightly coupled to FPGA placement and routing and there-
fore cannot be documented here. However, this design has been verified to route in ORCA FPGAs at a Generic
FIFO Bridge clock maximum frequency of 100MHz. Consider the following characteristics about the interface in
designing circuits to read and write frames from/to the Generic FIFO Bridge interface: 1) all outputs are clocked by
the rising edge of the clock, 2) all inputs are sampled by the rising edge of the clock, 3) all outputs originate at Q
outputs (sequential), 4) all inputs should be driven by sources that originate at Q outputs.
The table below lists various hardware aspects of the IP core’s Generic FIFO Bridge interface signals.
The following figures show timing diagrams for a 64-byte payload read from the Generic FIFO Bridge interface.
Note that due to a peculiar characteristic of the Block RAM based FIFO of the ORCA Series 4, read transfer timing
differs between the first read after the FIFO is empty and a read anytime thereafter. The two cases are shown
below.
Name Description Min. Max.
tclk_freq
Clock frequency — 100MHz
tclk_period Clock period 10ns —
tclk_signal_valid Signal valid from rising edge of clock 0.5ns 2.4ns
Name Description Min. Typ. Max.
V
DDIO
I/O supply voltage
2.3V
2.5V 2.7V
V
OH
V
OUT
high voltage
V
DDIO
- 0.2V
— —
V
OL
V
OUT
low voltage — —
0.2V
I
OH
I
OUT
at V
OH
12mA — —
I
OL
I
OUT
at V
OL
6mA — —
c6_clk_out_N_ext
c6_sof_out_N_ext
c6_parity_out_N_ext
c6_data_out_N_ext[31:0]
1,2,3 5,6,7
65,66,
67,68
69,70,
71,72
tclk_period
c6_clk_out_N_ext
c6_signal_out_N_ext
tclk_signal_valid
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

CSIX-LEV1-O4-N1

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Manufacturer:
Lattice
Description:
Development Software CSIX Level 1
Lifecycle:
New from this manufacturer.
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