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CSIX-LEV1-O4-N1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
Lattice Semiconductor CSIX Level 1 IP Core User’s Guide
7
network element to pause transmission on the inbound data path, thereby preventing the inbound FIFO from over-
flowing.
The fourth flow control mechanism is associated with the outbound FIFOs. If either of the associated “near-full” sig-
nals is asserted, the inbound path deasserts the local control/data ready signal. This should signal the user appli-
cation or remote CSIX element to pause transmission on the outbound path, thereby preventing the outbound
FIFOs from overflowing.
Port Aggregation
The core supports port aggregation. If an application instantiates more than one 32-bit CSIX core, two or more
cores can be aggregated into a larger CSIX interface. For example, two cores can be aggregated to operate as a
64-bit CSIX interface, three cores can operate as a 96-bit interface, and four cores can operate as a 128-bit inter-
face. Proper operation of the port aggregation mode requires that the external CSIX ports conform to the clock
domain skew limits listed in the CSIX-L1 Specification. Also, the internal user application for the CSIX core must
use a single timing domain to clock the aggregated cores.
Three user parameters control the configuration of port aggregation:
1. Port_Aggregation (yes, no)
2. Aggregation_Span_0 (2,3,4)
3. Aggregation_Span_1 (0,2)
If port aggregation is to be instantiated, then the first parameter must be yes. If aggregation is instantiated, then the
last two parameters must be specified. Typically, only one aggregation function will be specified (Span_0). How-
ever, if four cores are instantiated for an application, it is possible to create two 64-bit CSIX interfaces. In this case
Span_0 = 2, and Span_1 = 2. The highest numbered core is always the most significant 32-bit group of the aggre-
gate. The other cores decrease in precedence, down to core 0 as the least significant group.
Register Interface
A bank of registers is implemented to manage various programmable control functions and store various error and
status signals. These registers are controlled by a register interface that is compatible with the ORCA system bus
interface as shown in Figure 1. When a user instantiates an ORCA
®
SYSBUS slave interface to control the core
registers, the external FPGA control interface is compatible with a Motorola MPC860 Power PC interface. The
description below is specific to this IP core. Therefore, the bus widths may not match the generic bus widths shown
in Figure 1.
The core maintains an 8-bit implementation of the system bus. A 9-bit address bus (us_addr[8:0]) specifies the
locations of the registers (0x000 - 0x1FF). An active low
us_ready
signal enables a register access cycle. An
us_wr
signal enables writing when high, reading when low. Data to be written to registers appears on the 8-bit bus
“us_wdata[7:0]”. Data read from registers appears on the 8-bit bus “us_rdata[7:0]”, and is driven only during access
to one of the implemented registers. The
us_clk
signal synchronizes register accesses and can be any frequency
up to 50MHz. The active high
us_ack
signal asserts when the core is ready to end the current bus cycle.
Lattice Semiconductor CSIX Level 1 IP Core User’s Guide
8
Register Descriptions
Table 3. Register Map
Register Name
Register Address Description
Global Control Register
0x8000 Holds global control functions
Reset Control Reg 0x8004 Resets logic for IP Channels [3:0]
FIFO Flush Control Reg 0x8008 Flushes all FIFOs for IP Channels [3:0]
Force H Parity Error Reg 0x800C Force Horizontal Par Errs for Channels[3:0]
Force V Parity Error Reg 0x8010 Force Vertical Par Errs for Channels[3:0]
Reserved 0x8014 - 0x801c Reserved
In Data Lo Watermark 0 0x8040 Low watermark for the inbound data FIFO, Channel 0
In Cntrl Lo Watermark 0 0x8044 Low watermark for the inbound cntrl FIFO, Channel 0
In Data Hi Watermark 0 0x8048 High watermark for the inbound data FIFO, Channel 0
In Cntrl Hi Watermark 0 0x804C High watermark for the inbound cntrl FIFO, Channel 0
Out Data Lo Watermark 0 0x8050 Low watermark for the outbound data FIFO, Channel 0
Out Cntrl Lo Watermark 0 0x8054 Low watermark for the outbound cntrl FIFO, Channel 0
Out Data Hi Watermark 0 0x8058 High watermark for the outbound data FIFO, Channel 0
Out Cntrl Hi Watermark 0 0x805C High watermark for the outbound cntrl FIFO, Channel 0
In Data Lo Watermark 1 0x8080 Low watermark for the inbound data FIFO, Channel 1
In Cntrl Lo Watermark 1 0x8084 Low watermark for the inbound cntrl FIFO, Channel 1
In Data Hi Watermark 1 0x8088 High watermark for the inbound data FIFO, Channel 1
In Cntrl Hi Watermark 1 0x808C High watermark for the inbound cntrl FIFO, Channel 1
Out Data Lo Watermark 1 0x8090 Low watermark for the outbound data FIFO, Channel 1
Out Cntrl Lo Watermark 1 0x8094 Low watermark for the outbound cntrl FIFO, Channel 1
Out Data Hi Watermark 1 0x8098 High watermark for the outbound data FIFO, Channel 1
Out Cntrl Hi Watermark 1 0x809C High watermark for the outbound cntrl FIFO, Channel 1
In Data Lo Watermark 2 0x80C0 Low watermark for the inbound data FIFO, Channel 2
In Cntrl Lo Watermark 2 0x80C4 Low watermark for the inbound cntrl FIFO, Channel 2
In Data Hi Watermark 2 0x80C8 High watermark for the inbound data FIFO, Channel 2
In Cntrl Hi Watermark 2 0x80CC High watermark for the inbound cntrl FIFO, Channel 2
Out Data Lo Watermark 2 0x80D0 Low watermark for the outbound data FIFO, Channel 2
Out Cntrl Lo Watermark 2 0x80D4 Low watermark for the outbound cntrl FIFO, Channel 2
Out Data Hi Watermark 2 0x80D8 High watermark for the outbound data FIFO, Channel 2
Out Cntrl Hi Watermark 2 0x80DC High watermark for the outbound cntrl FIFO, Channel 2
In Data Lo Watermark 3 0x8100 Low watermark for the inbound data FIFO, Channel 3
In Cntrl Lo Watermark 3 0x8104 Low watermark for the inbound cntrl FIFO, Channel 3
In Data Hi Watermark 3 0x8108 High watermark for the inbound data FIFO, Channel 3
In Cntrl Hi Watermark 3 0x810C High watermark for the inbound cntrl FIFO, Channel 3
Out Data Lo Watermark 3 0x8110 Low watermark for the outbound data FIFO, Channel 3
Out Cntrl Lo Watermark 3 0x8114 Low watermark for the outbound cntrl FIFO, Channel 3
Out Data Hi Watermark 3 0x8118 High watermark for the outbound data FIFO, Channel 3
Out Cntrl Hi Watermark 3 0x811C High watermark for the outbound cntrl FIFO, Channel 3
FIFO Underflow Errors 0x8140 FIFO underflow error status for Channels[3:0]
FIFO Overflow Errors 0x8144 FIFO overflow error status for Channels[3:0]
Parity Errors 0x8148 Horizontal and vertical parity errors for Channels[3:0]
Miscellaneous Errors 0x814C Receiver synchronization error
Lattice Semiconductor CSIX Level 1 IP Core User’s Guide
9
Detailed Register Descriptions
Address:
0x8000
Name:
Global Control Register
D7
D6 D5 D4 D3 D2 D1 D0
— — — — Reset Enable
H_Parity
Enable
V_Parity
Enable
Transmission
Enable
Default value: 0x01 Mode: Read/Write
Description:
Transmission_Enable
When high, CSIX and SINE transmission logic is enabled to operate for all instantiated
channels.
V_Parity_Enable
When high, vertical parity error detectors on inbound CSIX ports are enabled to operate for all
instantiated channels.
H_Parity _Enable
When high, horizontal parity error detectors on inbound CSIX ports are enabled to operate for
all instantiated channels.
Reset_Enable
When high, this bit initializes all registers and resets all transmission logic. Note that this reset
function is self clearing.
Address:
0x8004
Name:
Reset Control Register
D7
D6 D5 D4 D3 D2 D1 D0
— — — — Reset_3 Reset_2 Reset_1 Reset_0
Default value: 0x00 Mode: Read/Write
Description:
Reset_N When high, transmission logic for channel N is reset. Note that this bit is not self clearing. The
bit must be written to 0 to deassert the associated reset.
Address:
0x8008
Name:
FIFO Flush Register
D7 D6 D5 D4 D3 D2 D1 D0
— — — — Flush_3 Flush_2 Flush_1 Flush_0
Default value: 0x00 Mode: Read/Write
Description:
Flush_N When high, all FIFOs for channel N are flushed. Note that this bit is not self clearing. The bit
must be written to zero to deassert the associated flush.
Address:
0x800C
Name:
Force H Parity Error Register
D7
D6 D5 D4 D3 D2 D1 D0
— — — —
Force
HPERR_3
Force
HPERR_2
Force
HPERR_1
Force
HPERR_0
Default value: 0x00 Mode: Read/Write
Description:
Force_HPERR_N When high, the horizontal parity checker on channel N is forced to detect a parity error. Note
this bit is not self clearing. The bit must be written to zero to deassert the associated error con-
dition.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

CSIX-LEV1-O4-N1

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Development Software CSIX Level 1
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