10
FN6830.0
December 19, 2008
Bias and Charge Pump Voltages:
The BIAS pin feeds the chip bias voltage directly to the first
of the two internal charge pumps, which are cascaded. The
output of the first charge pump, in addition to feeding the
second charge pump, is accessible on the CPVDD pin. The
voltage on the CPVDD pin is approximately 5V. It also
provides power to the POR and band-gap circuitry as shown
in the block diagram. A capacitor connected externally
across CPQ+ and CPQ- pins of the IC is the “flying” cap for
the charge-pump.
The second charge-pump is used exclusively to drive the
gates of the MOSFETs during soft start through the 24µA
current sources, one for each channel. The output of this
charge pump is approximately 10V as shown in the “Block
Diagram” on page 2.
Typical Hot-plug Power Up Sequence
1. When power is applied to the IC on the BIAS pin, the first
charge pump immediately powers up.
2. If the BIAS voltage is 2.1V or higher, the IC comes out of
POR. Both SS and TCB caps remain discharged and the
gate (GT) voltage remains low.
3. ENx pin, when pulled below it’s specified threshold,
enables the respective channel.
4. SSx cap begins to charge up through the internal 10µA
current source, the gate (GT) voltage begins to rise and
the corresponding output voltage begins to rise at the
same rate as the SS cap voltage. This is tightly controlled
by the soft-start amplifier shown in the block diagram.
5. SS cap begins to charge but the corresponding TCBx cap
is held discharged.
6. Fault (FLT) remains deasserted (stays high) and the
output voltage continues to rise.
7. If the load current on the output exceeds the set current
limit for greater than the circuit breaker delay, FLT
gets
asserted and the channel shutdown occurs.
8. If the voltage on UV pin exceeds 633mV threshold as a
result of rising Vo, the Power Good (PG) output goes
active.
9. At the end of the SS interval, the SS cap voltage reaches
CPVDD and remains charged as long as EN remains
asserted or there is no other fault condition present that
would attempt to pull down the gate.
Applications Information
Selection of External Components
The typical application circuit of Figure 2 has been used for
this section, which provides guidelines to select the external
component values.
MOSFET (Q1)
This component should be selected on the basis of its
r
DS(ON)
specification at the expected Vgs (gate to source
voltage) and the effective input gate capacitance (Ciss). One
needs to ensure that the combined voltage drop across the
Rsense and r
DS(ON)
at the desired maximum current
(including transients) will still keep the output voltage above
the minimum required level.
Ciss of the MOSFET influences the overcurrent response
time. It is recommended that a MOSFET with Ciss of less
than 10nF be chosen. Ciss will also have an impact on the
SS cap value selection as seen later.
Current Sense Resistor (R
SNS
)
The voltage drop across this resistor, which represents the
load current (Io), is compared against the set threshold of
the Circuit Breaker comparator. The value of this resistor is
determined by how much combined voltage drop is tolerable
between the source and the load. It is recommended that at
least 20mV drop be allowed across this resistor at max load
current. This resistor is expected to carry maximum full load
current indefinitely. Hence, the power rating of this resistor
must be greater than I
O(MAX)
2
*R
SNS
.
This resistor is typically a low value resistor and hence the
voltage signal appearing across it is also small. In order to
maintain high current sense accuracy, current sense trace
routing is critical. It is recommended that either a four wire
resistor or the routing method as shown in Figure 17 be
used.
Q
Rsns
R
SET
VS1
SNS1
GT1
-
+
I
o
I
SET
V
IN
V
O
+
-
+
-
ISL6174
25Ω
WOC
COMPARATOR
GATE
PULLDOWN
CURRENT
FIGURE 16. OC / WOC OPERATION
-
+
3k
OC COMPARATOR
ISL6174
11
FN6830.0
December 19, 2008
Current Set Resistor (R
SET
)
This resistor sets the threshold for the Circuit Breaker
comparator in conjunction with R
SNS
. Once R
SNS
has been
selected, use Equation 1 to calculate R
SET
. Use 20µA for
I
SET
in a typical application.
Reference Current Set Resistor (R
REF
)
This resistor sets up the current in the internal current
source, I
REF
/4, shown in Figure 2 for the comparators. The
voltage at the OCREF pin is the same as the internal
bandgap reference. The current (I
REF
) flowing through this
resistor is simply:
I
REF
= 1.178/R
REF
This current, I
REF
, should be set at 80µA to force 20µA in the
internal current source as shown in Figure 2, because of the
4:1 current mirror. This equates to the resistor value of
14.7k.
Selection of Rs1 and Rs2
These resistors set the UV detect point. The UV comparator
detects the undervoltage condition when it sees the voltage
at UV pin drop below 0.633V. The resistor divider values
should be selected accordingly.
Charge Pump Capacitor Selection (C
P
and C
V
)
C
P
is the “flying cap” and C
V
is the smoothing cap of the
charge pump, which operates at 450kHz set internally. The
output resistance of the charge pump, which affects the
regulation, is dependent on the C
P
value and its ESR,
charge-pump switch resistance, and the frequency and ESR
of the smoothing cap, C
V
.
It is recommended that C
P
be kept within 0.022µF
(minimum) to 0.1µF (maximum) range. Only ceramic
capacitors are recommended. Use 0.1µF cap if CPVDD
output is expected to power an external circuit, in which case
the current draw from CPVDD must be kept below 10mA.
C
V
should at least be 0.47µF (ceramic only). Higher values
may be used if low ripple performance is desired.
Time-out Capacitor Selection (C
T
)
This capacitor determines the current regulation delay
period. As shown in Figure 2, when the voltage across this
capacitor exceeds 1.178V, the time-out comparator detects it
and the gate voltage is pulled to 0V thus shutting down the
channel. An internal 10µA current source charges this
capacitor. Hence, the value of this capacitor is determined by
Equation 2.
Where,
T
OUT
= Desired time-out period.
Soft-Start Capacitor Selection (C
SS
)
The rate of change of voltage (dv/dt) on this capacitor, which
is determined by the internal 10µA current source, is the
same as that on the output load capacitance. Hence, the
value of this capacitor directly controls the inrush current
amplitude during hot swap operation.
Where,
C
O
= Load Capacitance
I
INRUSH
= Desired Inrush Current
I
INRUSH
is the sum of the DC steady-state load current and
the load capacitance charging current. If the DC steady-state
load remains disabled until after the soft-start period expires
(PGx
could be used as a load enable signal, for example),
then only the capacitor charging current should be used as
I
INRUSH
. The Css value should always be more than (1/2.4)
of that of Ciss of the MOSFET to ensure proper soft-start
operation. This is because the Ciss is charged from 24µA
current source, whereas the Css gets charged from a 10µA
current source (Figure 15). In order to make sure both V
SS
and V
O
track during the soft-start, this condition is
necessary.
ISL6174 Evaluation Platform
The ISL617XEVAL1Z is the primary evaluation board for this
IC. For the BOM, schematic and photograph, see the “BOM
for ISL617XEVAL1Z Board and Schematic” on page 15.
The evaluation board has been designed with a typical
application in mind and with accessibility to all the featured
pins to enable a user to understand and verify these features
of the IC. The two circuit breaker levels are programmed to
2.2A for each input rail but they can easily be scaled up or
down by adjusting some component values.
There are two input voltages, one for each channel that are
switched by a dual N-Channel MOSFET (Q1) to the output
connectors.
LOAD CURRENT CARRYING
TRACES
R
SNS
CURRENT
SENSE
TRACES
FIGURE 17. RECOMMENDED CURRENT SENSE RESISTOR
PCB LAYOUT
C
T
10μAT
OUT
()1.178=
(EQ. 2)
C
SS
C
O
10μAI
INRUSH
()=
(EQ. 3)
ISL6174
12
FN6830.0
December 19, 2008
Pins SS1 and SS2 of the IC are available as jumper test
points so that they can be tied together to achieve
concurrent tracking between Vo1 and Vo2. Both the EN
inputs must be turned on together to check this function,
jumpers are provide to facilitate this.
Each channel is preloaded with the resistive load that makes
up the UV threshold level. Additional loading can be
externally applied as desired.
The internal Circuit Breaker amplifier is fast enough to
respond to very fast di/dt events.
On this board, the timeout capacitor value for side ‘1’ is
0.15µF, which corresponds to a timeout period of 17.67ms.
The scope shots are taken from the ISL6174EVAL1 to
demonstrate the ISL6174s critical operational waveforms.
Figure 18 illustrates the circuit breaker operation which will
be evident with a slow ramping output current at the
programmed 2.2A level, I
CB
. This mode of operation will be
invoked while the OC event is < ~2X the I
CB
. as shown in
Figure 19. Characteristic of this operational mode is the TCB
pin ramping to V
CB
to establish the circuit breaker delay.
The way to confirm WOC mode, is by looking at the TCB pin
waveform. If no ramping is seen prior to GATE turn off, then
WOC is active. The following waveform in Figure 20 shows
WOC operation:
:
Figure 21 is a 200X zoom of a WOC turn-off event and
clearly illustrates the lack of any TCB ramping during this
WOC event.
FIGURE 18. SLOW RAMPING TO 2.2A OC CIRCUIT BREAKER
OPERATION
TCB
Iin
GATE
FIGURE 19. TRANSIENT TO 3.9A OC CIRCUIT BREAKER
OPERATION
GATE
TCB
Iin
FIGURE 20. WOC CIRCUIT BREAKER OPERATION
GATE
TCB
Iin
ISL6174

ISL6174IRZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Hot Swap Voltage Controllers W/ANNL DL LV CIRCUIT BREAKER
Lifecycle:
New from this manufacturer.
Delivery:
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