DS33M33N+ Datasheet DS33M30N+, DS33M31N+, DS33M33N+ | P10-P12

DS33M30/M31/M33 DATA SHEET

Rev: 010809 10 of 21

1.3.7.2

STS-1/AU-3/TU-3 Pointer Interpreter

• Per STS-1/AU-3/TU-3 tributary pointer interpretation using the outbound Drop STS-3/STM-1 clock

• Pointer interpretation per Telcordia GR-253-CORE and ITU G.707 specifications

• Extraction of STS-1, AU-3, or TU-3 pointer bytes (H1, H2, and H3)

• Detection of defects including, LOP and “all-ones” pointer (AIS-P)

• Detection and accumulation of incoming pointer increments, decrements, changes, and new pointers

1.3.8

STS-1/VC-3 Path Termination (DS33M31 and DS33M33 only)

1.3.8.1

STS-1/VC-3 Path Overhead Generation

• Generation of all POH bytes including Path trace ID (J1), Path BIP-8 (B3), Path signal label (C2), Path

status (G1), Path user byte (F2), Path concatenation indicator (H4), and Path growth (Z3, Z4, and Z5)

• All POH bytes can be inserted from either the associated inbound Add STS-1/VC-3 POH input port or

software accessible internal registers

• Automatic or manual generation of PTE alarm defects including RDI-P and ERDI-P

• Programmable error insertion of B3 and REI errors

• Insertion of HDLC data stream into path user byte (F2)

• Insertion of path trace ID into path trace byte (J1)

1.3.8.2

STS-1/VC-3 Path Overhead Reception and Monitoring

• Termination of all POH bytes (per PTE requirement) including Path trace ID (J1), Path BIP-8 (B3), path

signal label (C2), Path status (G1), Path user byte (F2), path concatenation indicator (H4), and Path growth

(Z3, Z4, and Z5)

• All POH bytes presented on the associated STS-1 SPE/VC-3 POH output port and software accessible

internal registers

• Detection of PTE defects: PLM-P, PLU-P, UNEQ-P, PDI-P, RDI-P, and Enhanced RDI-P (ERDI-P)

• Detection and accumulation of path B3 and path REI errors (part of G1) on a bit or block basis

• Two POH B3 bit error rate (BER) measurement circuits with separate software programmable detection

and clearing thresholds

• Extraction of HDLC data stream from path user byte (F2)

• Extraction of path trace ID from path trace byte (J1)

1.3.8.3

STS-1/VC-3 Synchronizer

• Synchronization of STS-1 SPE/VC-3 to accommodate asynchronous payload through pointer justifications

• Accommodation of frequency offsets up to +100ppm between the SONET/SDH Telecom Bus reference

frequency of 77.76MHz and the line/tributary STS-1 frequency 51.84MHz

• Elastic store overflow and underflow conditions

• Selectable lock and fast lock modes of operation

• Programmable frequency out of range indication (±5, ±10, ±20, or ±40ppm).

• SONET mapping jitter conforming to GR-253 and GR-499 and SDH mapping jitter compliant to ITU G.825e

and O.172e

1.3.8.4

STS-1 SPE Payload Mapping

• Each STS-1 SPE can be mapped with Asynchronous DS3/E3 or Ethernet traffic. These two mapping

modes are mutually exclusive.

1.3.8.5

STS-1 SPE Ethernet Mapping/Demapping

• Mapping of Ethernet packets into STS-1 SPE

1.3.8.6

Async DS3/E3 Demapper/Desynchronizer

• Extraction of DS3/E3 data stream from an STS-1 SPE compliant to Telcordia GR-253 or VC-3 compliant to

ITU G.707

• Generation of a nominal rate E3 (34.368MHz) or DS3 (44.736MHz)

• Standard SONET STS-1 demapping for a DS3/E3 conforming with Telcordia GR-253 and GR-499

• Standard SDH VC-3 demapping for a DS3/E3 conforming to ITU-T G.707, G.825e, and O.172e

• All combinations of DS3 or E3 demapping configuration from STS-1, AU-3, or TU-3/AU-4 are possible

• Software configuration for SONET/SDH demapping on a per tributary basis

DS33M30/M31/M33 DATA SHEET

Rev: 010809 11 of 21

• Synchronization of DS3/E3 serial streams from SONET/SDH STS-1 SPE/VC-3 accommodating

asynchronous timing between the DS3/E3 line/tributary and the STS-3/STM-1 references, through

appropriate processing of bit stuffing and pointer justifications

• Full integration of the DS3/E3 desynchronization and PLL circuitry necessary to produce smooth DS3/E3

data and clock signals that meet the Telcordia (GR-253-CORE and GR-499-CORE), ANSI (T1-105.03-

1994 and T1-105.03b-1997), and ITU (G.825e and O.172e) jitter and wander requirements. Desynchronize

circuitry includes clock smoother consisting of onboard analog/digital control modulators, analog/digital

filters, and frequency detectors

• Absorption of SONET/SDH pointer justifications and DS3/E3 payload bit stuffs in an elastic store, and

controlling outgoing clock phase using the smooth clock generator circuit with selectable lock and fast lock

modes of operation

• Tolerating frequency offsets up to ±200ppm between the inbound Add Telecom Bus clock (ACLK) and the

free-running DS3/E3 reference clocks generated by the internal Clock Rate Adapter

• Monitoring and detection of the stability of the recovered DS3 clocks with frequency offset indications of

±20, ±100, and ±200ppm and the elastic store FIFO underflow/overflow conditions. The elastic store has

an auto center mechanism that separates the read and write pointers under normal operating conditions

and after underflow/overflow events occur

• Programmable frequency out of range indication (±10, ±20, ±40, or ±100ppm)

• Selectable lock and fast lock modes of operation

• Maximum lock time for the smooth recovered/output DS3/E3 data and clock that is demapped from

SONET/SDH is 1.06ms (10 DS3, 24 G.751 E3, or nine G.832 E3 frames) (switch time to valid DS3 with a

smooth clock)

• Controls include enables/disables/settings for serial data type, and demapping mode

1.3.8.7

Async DS3/E3 Mapper/Synchronizer

• Synchronization of DS3/E3 serial streams to SONET/SDH STS-1 SPE/VC-3 accommodating

asynchronous timing between the DS3/E3 line/tributary and the STS-3/STM-1 references, through bit

stuffing

• Accommodation of frequency offsets up to +200ppm between the 155.52Mbps inbound add STS-3/STM-1

serial data stream and the 44.736/34.368MHz line/tributary DS3/E3 clock (RLCLKn)

• Elastic store overflow and underflow conditions

• Programmable frequency out of range indication (±10, ±20, ±40, or ±100ppm)

• SONET mapping jitter conforming to GR-253 and GR-499 and SDH mapping jitter compliant to ITU G.707,

G.825e and O.172e

• Mapping of DS3/E3 serial data stream into an STS-1 SPE compliant to Telcordia GR-253 or VC-3

compliant to ITU G.707

• Standard SONET STS-1 mapping for DS3/E3 conforming to Telcordia GR-253 and GR-499

• Standard SDH VC-3 mapping for DS3/E3 conforming to ITU-T G.707

• All combinations of DS3 or E3 mapping configuration into STS-1, AU-3, or TU-3/AU-4 are possible

• Software configuration for SONET/SDH mapping on a per tributary basis

• Software configuration for all fixed stuff bits to zeros or ones

• Controls include enables/disables/settings for mapping type, alarm insertion, stuff bits, frequency offset

(±100ppm to ±200ppm)

DS33M30/M31/M33 DATA SHEET

Rev: 010809 12 of 21

1.4

PDH (DS33M31 and DS33M33 Only)

There are two sets of DS3/E3 framer/formatters. Each set supports three independent DS3/E3 data streams (or

ports). The set interfaces directly to the Async DS3/E3 mapper called Add/Drop Framer/Formatter. The set

interfaces with external T3/E3 facilities are called Line Framer/Formatter The Add/Drop Framers reside in both the

DS33M31 and DS33M33 and are used for path monitoring the desynchronized DS3/E3 and test origination of the

PDH signals. The Line Framers, supported only in DS33M33, are used for path monitoring the received signals

from external facilities.

1.4.1

Add/Drop DS3/E3 Framer/Formatter (DS33M31 and DS33M33 only)

1.4.1.1

Drop DS3/E3 Framer

• Incorporation of drop DS3/E3 framers on a per port basis for far-end alarm detection and performance

monitor of DS3/E3 signals that are demapped from SONET/SDH STS-12/STM-4

• Frame synchronization for M23 DS3, C-bit Parity DS3, G.751 E3, and G.832 E3

• Detection of DS3 loss of frame (LOF), out of frame (OOF), out of multiframe (OOMF), severely error frame

(SEF), change of frame alignment (COFA), remote defect indication (RDI), alarm indication signal (AIS),

receive unframed all ones, idle signal, DS3 application ID bit, and DS3 format mismatch

• Detection of G.751 E3 LOF, OOF, COFA, remote alarm indication (RAI), and AIS

• Detection of G.832 E3 LOF, OOF, COFA, RDI, and AIS

• Detection and accumulation of F-bit errors, M-bit errors, FAS errors, FA1 and FA2 byte errors, OOF

occurrences, P-bit parity errors, C-bit parity errors, BIP-8 (bit or block basis) errors, far end block errors

(FEBE), and remote error indications (REI)

• Fully programmable automatic AIS insertion upon detection of OOF and/or AIS

• All DS3/E3 overhead fields are presented on the associated receive DS3/E3 overhead output port

• Extraction of HDLC data stream from DS3 path maintenance data link (PMDL), G.751 E3 national bit, or

G.832 E3 NR or GC bytes

• Extraction of trail trace access point identifier from G.832 E3 TR byte

1.4.1.2

Add DS3/E3 Formatter (Optional)

• Insertion of all overhead for M23 DS3, C-bit parity DS3, G.751 E3, and G.832 E3

• Manual generation of AIS and DS3 idle signals

• Automatic or manual generation of RDI/RAI and FEBE/REI

• Programmable error insertion of framing errors, parity errors, and FEBE/REI errors

• All DS3/E3 overhead fields can be sourced from the external transmit DS3/E3 overhead input port

• Insertion of HDLC data stream into DS3 path maintenance data link (PMDL), G.751 E3 national bit, or

G.832 E3 NR or GC bytes

• Insertion of trail trace access point identifier into G.832 E3 TR byte

• M23 DS3 C-bits programmable as payload or overhead

• Formatter pass-through mode with programmable DS3 P-bit correction for DS3/E3 line terminating

equipment (LTE) applications

1.4.1.3

HDLC Controller

• Two controllers per port for DS3 path maintenance data link (PMDL), G.751 national bit (Sn), G.832

NR/GC, or STS-1 DCCs (D1-D3 and/or D4-12), or STS-1/VC-3 path user channel (F1 or F2)

• A controller for each optional VC-4 path user channels (F2)

• 256-byte receive and transmit FIFOs

• Handles all of the normal Layer 2 tasks including zero stuffing/destuffing, FCS generation/checking, abort

generation/checking, flag generation/detection, and byte alignment

• Programmable high and low water marks for the transmit and receive FIFOs

• Rx data is forced to all ones during LOS, LOF, and AIS detection to eliminate false packets

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

DS33M33N+

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Buy DS33M33N+

Manufacturer:

Maxim Integrated

Description:

Telecom Interface ICs Ethernet Over SONET/SDH Mapper

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DS33M33N+

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