DS33M30/M31/M33 DATA SHEET
Rev: 010809 4 of 21
1.
General Description and Feature Highlights
The DS33M30 family of devices provides interconnection and mapping functionality between Ethernet and
SONET/SDH networking elements. The product family includes three devices with differing features:
• DS33M30: One GMII mapped to STS-3c/VC-4 in a compact 10mm package.
• DS33M31: One GMII/MII mapped to a protected interface, with higher order EoS and EoPoS.
• DS33M33: One GMII/MII mapped to a protected interface, with higher order EoS, EoPoS and DS3/E3
add/drop mux.
All devices in the product family contain an Ethernet MAC port, one or two STS-3/STM-1 SerDes ports with the
LVDS/LVPECL interface, one or three GFP-F/HDLC/cHDLC/X.86 (LAPS) protocol encapsulators, one or three
higher order SONET/SDH mappers, a DDR SDRAM interface, and a local bus port for control/status. Ethernet
traffic is encapsulated with GFP-F, HDLC, cHDLC, or X.86 (LAPS) protocol to be transmitted onto the STS-3/
STM-1 interface. The family receives encapsulated Ethernet frames from the SerDes receiver interface and
transmits the de-encapsulated frames onto the Ethernet port.
With the smallest footprint, the DS33M30 contains the smallest feature set in the product family. It performs EoS
higher order mapping of Ethernet frames into a single STS-3c SPE or VC-4. The DS33M30 has one 1000Mbps
(GbE) port with GMII interface. The DS33M30 supports Ethernet OAM insert/extract capability, QoS Priority
Scheduling, VLAN processing, and committed information rate (CIR)-based policers for the delivery of carrier
Ethernet services.
The DS33M31 and DS33M33 expand on the features of the DS33M30 with additional mapping capabilities. They
support next-generation Ethernet over SONET/SDH in virtually concatenated higher order containers as well as
Ethernet-over-PDH-over-SONET/SDH (EoPoS) at the DS3/E3 level. They have an Ethernet interface that can be
configured as a 10/100Mbps MII/RMII port or a 1000Mbps (GbE) GMII port. They integrate four
mapping/demapping functions:
• SONET/SDH mapping: STS-1/VC-3 to STS-3/STM-1; or TU-3 to VC-4 to STM-1
• PDH mapping: DS3/E3 to STS-1/VC-3 (or TUG-3/VC-4);
• EoS higher order mapping: Ethernet to STS-1/VC-3 (or TU-3); and
• EoPoS mapping: Ethernet to DS3/E3 to STS-1/VC-3 (or TUG-3/VC-4).
At the STS-3/STM-1 side, the DS33M31 and DS33M33 devices interface to an STS-3/STM-1 signal through dual
serial-data buses operating at the rate of 155.52Mbps. This allows the implementation of a protected SONET/SDH
at PHY layer. Each serializer/deserializer (SerDes) is supported with independent STS-3/STM-1 framer.
The DS33M33 supports all the features of the DS33M30 and DS33M31, with additional line interfaces for up to
three add/drop DS3/E3 tributaries.
The SerDes interfaces, with LVDS/LVPECL, can be seamlessly connected to commercially available optical
transceivers.
Microprocessor control can be accomplished through an 8/16-bit local bus or SPI bus. The family contains a
125MHz DDR SDRAM controller and interfaces to a 32-bit-wide 256Mb DDR SDRAM through a 16-bit data bus.
The DDR SDRAM is used to buffer data through the Ethernet and STS-3/STM-1 ports.
The power supplies consist of a 1.8V core supply, a 2.5V DDR SDRAM supply, and 3.3V I/O supply.
