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ADG212AKRZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LC
2
MOS
Quad SPST Switches
Data Sheet
ADG211A/ADG212A
Rev. C Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
44 V supply maximum rating
±15 V analog signal range
Low R
ON
: 115 Ω maximum
Low leakage: 0.5 nA typical
Break-before-make switching
Single supply operation possible
Extended plastic temperature range: −40°C to +85°C
TTL/CMOS compatible
Available in 16-lead PDIP/SOIC and 20-pead PLCC packages
Pin compatible to DG211/DG212
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
Figure 2.
GENERAL DESCRIPTION
The ADG211A and ADG212A are monolithic CMOS devices
comprising four independently selectable switches. They are
designed on an enhanced LC
2
MOS process, which gives an
increased signal handling capability of ±15 V. These switches
also feature high switching speeds and low R
ON
.
The ADG211A and ADG212A consist of four SPST switches.
They differ only in that the digital control logic is inverted. In
multiplexer applications, all switches exhibit break-before-make
switching action when driven simultaneously. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
PRODUCT HIGHLIGHTS
1. Extended Signal Range.
These switches are fabricated on an enhanced LC
2
MOS
process, resulting in high breakdown and an increased
analog signal range of ±15 V.
2. Single Supply Operation.
For applications where the analog signal is unipolar (0 V to
15 V), the switches can be operated from a single 15 V
supply.
3. Low Leakage.
Leakage currents in the range of 500 pA make these
switches suitable for high precision circuits. The added
feature of break-before-make allows for multiple outputs
to be tied together for multiplexer applications while
keeping leakage errors to a minimum.
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
ADG211A
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D4
S4
D3
10950-001
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
ADG212A
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D4
S4
D3
10950-002
ADG211A/ADG212A Data Sheet
Rev. C | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
ESD Caution...................................................................................4
Pin Configurations and Function Descriptions ............................5
Typical Performance Characteristics ..............................................6
Terminolog y .......................................................................................9
Test Circuits ..................................................................................... 10
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 13
REVISION HISTORY
10/12—Rev. B to Rev. C
Updated Format .................................................................. Universal
Added Pin Descriptions, Table 3 .................................................... 5
Moved Table 4 ................................................................................... 5
Changes to Figure 5, Figure 6, Figure 8, and Figure 9 ................. 6
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
9/02—Rev. A to Rev. B
Data Sheet ADG211A/ADG212A
Rev. C | Page 3 of 16
SPECIFICATIONS
V
DD
= +15 V, V
SS
= −15 V, V
L
= 5 V, unless otherwise noted.
Table 1.
Parameter
25°C −40°C to +85°C
Unit Test Conditions/Comments Min Typ Max Min Typ Max
ANALOG SWITCH
Analog Signal Range ±15 ±15 V
R
ON
115 175 Ω −10 V ≤ V
S
≤ +10 V, I
DS
= 1 mA, see Figure 21
R
ON
vs. V
D
(V
S
) 20 %
R
ON
Drift 0.5 %/°C
R
ON
Match 5 % V
S
= 0 V, I
DS
= 1 mA
LEAKAGE CURRENTS
I
S
(Off) 0.5 nA
V
D
= ±14 V; V
S
=
14 V; see Figure 22
Off Input Leakage 5 100 nA
I
D
(Off) 0.5 nA
V
D
= ±14 V; V
S
=
14 V; see Figure 22
Off Output Leakage 5 100 nA
I
D
(On) 0.5 nA V
D
= V
S
= ±14 V; see Figure 23
On Channel Leakage 5 200 nA
DIGITAL CONTROL
V
INH
, Input High Voltage 2.4 V TTL compatibility is independent of V
L
V
INL
, Input Low Voltage 0.8 V
I
NL
or I
NH
1
C
IN
, Digital Input Capacitance 5 pF
DYNAMIC CHARACTERISTICS
t
OPEN
1
30
See Figure 24
t
ON
1
600 ns See Figure 25
t
OFF
1
450 ns See Figure 25
Off Isolation 80 dB
V
S
= 10 V (p-p); f = 100 kHz;
R
L
= 75 Ω; see Figure 26
Channel-to-Channel Crosstalk
80
See Figure 27
C
S
(Off) 5 pF
C
D
(Off) 5 pF
C
S
, C
D
(On) 16 pF
Q
INJ
, Charge Injection 20 pC R
S
= 0 Ω; C
L
= 1000 pF; V
S
= 0 V; see Figure 28
POWER SUPPLY
I
DD
0.6 mA Digital inputs = V
INL
or V
INH
I
DD
1 mA
I
SS
0.1 mA
I
SS
0.2
I
L
0.9 mA
1
Sample tested at 25°C to ensure compliance.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ADG212AKRZ

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Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs CMOS QUAD SPST IC
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