Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparators
ADCMP600/ADCMP601/ADCMP602
FEATURES
Fully specified rail to rail at V
CC
= 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to V
CC
+ 0.2 V
Low glitch CMOS-/TTL-compatible output stage
3.5 ns propagation delay
10 mW at 3.3 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 50 dB
Improved replacement for MAX999
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current/voltage-controlled oscillators
Automatic test equipment (ATE)
FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
INPUT
INVERTING
INPUT
LE/HYS
(EXCEPT ADCMP600)
Q OUTPUT
S
DN
(ADCMP602 ONLY)
ADCMP600/
ADCMP601/
ADCMP602
05914-001
Figure 1.
GENERAL DESCRIPTION
The ADCMP600, ADCMP601, and ADCMP602 are very fast
comparators fabricated on XFCB2, an Analog Devices, Inc.
proprietary process. These comparators are exceptionally
versatile and easy to use. Features include an input range from
GND − 0.5 V to V
CC
+ 0.2 V, low noise, TTL-/CMOS-compatible
output drivers, and latch inputs with adjustable hysteresis
and/or shutdown inputs.
The device offers 5 ns propagation delay with 10 mV overdrive
on 3 mA typical supply current.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a 0.5 V to +2.8 V
input signal range up to a +5.5 V positive supply with a −0.5 V
to +5.8 V input signal range. Split input/output supplies with no
sequencing restrictions on the ADCMP602 support a wide
input signal range while still allowing independent output
swing control and power savings.
The TTL-/CMOS-compatible output stage is designed to drive
up to 5 pF with full timing specs and to degrade in a graceful
and linear fashion as additional capacitance is added. The
comparator input stage offers robust protection against large
input overdrive, and the outputs do not phase reverse when the
valid input signal range is exceeded. Latch and programmable
hysteresis features are also provided with a unique single-pin
control option.
The ADCMP600 is available in 5-lead SC70 and SOT-23
packages, the ADCMP601 is available in a 6-lead SC70 package,
and the ADCMP602 is available in an 8-lead MSOP package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Fax: 781.461.3113 ©20062011 Analog Devices, Inc. All rights reserved.
ADCMP600/ADCMP601/ADCMP602
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Timing Information ......................................................................... 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Application Information ................................................................ 10
Power/Ground Layout and Bypassing ..................................... 10
TTL-/CMOS-Compatible Output Stage ................................. 10
Using/Disabling the Latch Feature ........................................... 10
Optimizing Performance ........................................................... 11
Comparator Propagation Delay Dispersion ........................... 11
Comparator Hysteresis .............................................................. 11
Crossover Bias Point .................................................................. 12
Minimum Input Slew Rate Requirement ................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 16
REVISION HISTORY
1/11Rev. 0 to Rev. A
Changed V
EE
Pin to GND ............................................. Throughout
Changes to Common-Mode Dispersion Conditions................... 4
Changes to Figure 15 and Figure 16 ............................................... 9
Changes to Comparator Hysteresis Section ................................ 12
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
10/06—Revision 0: Initial Version
ADCMP600/ADCMP601/ADCMP602
Rev. A | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
CCI
= V
CCO
= 2.5 V, T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
Voltage Range V
P
, V
N
V
CC
= 2.5 V to 5.5 V −0.5 V
CC
+ 0.2 V
Common-Mode Range V
CC
= 2.5 V to 5.5 V −0.2 V
CC
+ 0.2 V
Differential Voltage V
CC
= 2.5 V to 5.5 V V
CC
+ 0.8 V
Offset Voltage V
OS
−5.0 ±2 +5.0 mV
Bias Current I
P
, I
N
−5.0 ±2 +5.0 µA
Offset Current 2.0 +2.0 µA
Capacitance C
P
, C
N
1 pF
Resistance, Differential Mode 0.1 V to V
CC
200 700 kΩ
Resistance, Common Mode −0.5 V to V
CC
+ 0.5 V 100 350 kΩ
Active Gain A
V
85 dB
Common-Mode Rejection Ratio CMRR V
CCI
= 2.5 V, V
CCO
= 2.5 V,
V
CM
= −0.2 V to +2.7 V
50 dB
V
CCI
= 2.5 V, V
CCO
= 5.5 V 50 dB
Hysteresis (ADCMP600) 2 mV
Hysteresis (ADCMP601/ADCMP602) R
HYS
= 0.1 mV
LATCH ENABLE PIN CHARACTERISTICS
(ADCMP601/ADCMP602 Only)
V
IH
Hysteresis is shut off 2.0 V
CC
V
V
IL
Latch mode guaranteed 0.2 +0.4 +0.8 V
I
IH
V
IH
= V
CC
−6 +6 µA
I
OL
V
IL
= 0.4 V 0.1 +0.1 mA
HYSTERESIS MODE AND TIMING
(ADCMP601/ADCMP602 Only)
Hysteresis Mode Bias Voltage Current1 μA 1.145 1.25 1.35 V
Resistor Value Hysteresis = 120 mV 65 80 120 kΩ
Hysteresis Current Hysteresis = 120 mV −18 −12 −7 µA
Latch Setup Time t
S
V
OD
= 50 mV −2 ns
Latch Hold Time t
H
V
OD
= 50 mV 2.6 ns
Latch-to-Output Delay t
PLOH
, t
PLOL
V
OD
= 50 mV 27 ns
Latch Minimum Pulse Width t
PL
V
OD
= 50 mV 21 ns
SHUTDOWN PIN CHARACTERISTICS
(ADCMP602 Only)
V
IH
Comparator is operating 2.0 V
CCO
V
V
IL
Shutdown guaranteed −0.2 +0.4 +0.6 V
I
IH
V
IH
= V
CC
−6 6 µA
I
OL
V
IL
= 0 V 100 µA
Sleep Time t
SD
I
CCO
< 500 µA 20 ns
Wake-Up Time t
H
V
OD
= 100 mV, output valid 50 ns
DC OUTPUT CHARACTERISTICS V
CCO
= 2.5 V to 5.5 V
Output Voltage High Level V
OH
I
OH
= 8 mA, V
CCO
= 2.5 V V
CC
− 0.4 V
Output Voltage Low Level V
OL
I
OL
= 8 mA, V
CCO
= 2.5 V 0.4 V
Output Voltage High Level at 40°C V
OH
I
OH
= 6 mA, V
CCO
= 2.5 V V
CC
− 0.4 V
Output Voltage Low Level at40°C V
OL
I
OL
= 6 mA, V
CCO
= 2.5 V 0.4 V

ADCMP602BRMZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Comparators RR Fast 2.5-5.5V SGL-Supply TTL/CMOS
Lifecycle:
New from this manufacturer.
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