SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9456/D
Rev 1, 03/2002
1
Motorola, Inc. 2002
The MPC9456 is a 2.5V and 3.3V compatible 1:10 clock distribution
buffer designed for low-voltage mid-range to high-performance telecom,
networking and computing applications. Both 3.3V, 2.5V and dual supply
voltages are supported for mixed-voltage applications. The MPC9456
offers 10 low-skew outputs and a differential LVPECL clock input. The
outputs are configurable and support 1:1 and 1:2 output to input
frequency ratios. The MPC9456 is specified for the extended temperature
range of –40 to 85°C.
Features
Configurable 10 outputs LVCMOS clock distribution buffer
Compatible to single, dual and mixed 3.3V/2.5V voltage supply
Wide range output clock frequency up to 250 MHz
Designed for mid-range to high-performance telecom, networking and
computer applications
Supports high-performance differential clocking applications
Max. output skew of 200 ps (150 ps within one bank)
Selectable output configurations per output bank
Tristable outputs
32 ld LQFP package
Ambient operating temperature range of –40 to 85°C
Functional Description
The MPC9456 is a full static design supporting clock frequencies up to
250 MHz. The signals are generated and retimed on-chip to ensure
minimal skew between the three output banks.
Each of the three output banks can be individually supplied by 2.5V or 3.3V supporting mixed voltage applications. The FSELx
pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for
each of the three output banks. The MPC9456 can be reset and the outputs are disabled by deasserting the MR/OE
pin (logic
high state). Asserting MR/OE
will enable the outputs.
All control inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive
terminated 50 transmission lines. The clock input is low voltage PECL compatible for differential clock distribution support.
Please consult the MPC9446 specification for a full CMOS compatible device. For series terminated transmission lines, each of
the MPC9456 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7
mm
2
32-lead LQFP package.
FA SUFFIX
LQFP PACKAGE
CASE 873A–02
LOW VOLTAGE SINGLE OR
DUAL SUPPLY 2.5V AND 3.3V
LVCMOS CLOCK
DISTRIBUTION BUFFER
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MPC9456
MOTOROLA TIMING SOLUTIONS2
Figure 1. MPC9456 Logic Diagram
0
1
0
1
0
1
VCCA
QA2
GND
QA1
VCCA
QA0
GND
QC3
GND
QC2
VCCC
QC1
GND
GND
QB0
VCCB
QB1
GND
QB2
VCCB
VCCC
NC
VCC
PECL_CLK
PECL_CLK
FSELA
FSELB
FSELC
GND
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
MPC9456
V
CCB
is internally connected to V
CC
Figure 2. Pinout: 32–Lead Package Pinout (Top View)
MR/OE
QC0
VCCC
CLK ÷ 2
MR/OE
PCLK
PCLK
FSELA
FSELB
FSELC
QA0
QA1
QA2
QB0
QB1
QB2
QC0
QC1
QC2
QC3
CLK
Bank A
Bank B
Bank C
25k
25k
25k
25k
25k
25k
V
CC
/2
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MPC9456
TIMING SOLUTIONS 3 MOTOROLA
Table 1: Pin Configuration
Pin I/O Type Function
PECL_CLK,
PECL_CLK
Input LVPECL Differential clock reference
Low voltage positive ECL input
FSEL
A
, FSEL
B
, FSEL
C
Input LVCMOS Output bank divide select input
MR/OE Input LVCMOS Internal reset and output tristate control
GND Supply Negative voltage supply output bank (GND)
V
CCA
, V
CCB
*, V
CCC
Supply Positive voltage supply for output banks
V
CC
Supply Positive voltage supply core (VCC)
QA0 - QA2 Output LVCMOS Bank A outputs
QB0 - QB2 Output LVCMOS Bank B outputs
QC0 - QC3 Output LVCMOS Bank C outputs
*V
CCB
is internally connected to V
CC
.
Table 2: Supported Single and Dual Supply Configurations
Supply voltage configuration V
CC
a
V
CCA
b
V
CCB
c
V
CCC
d
GND
3.3V 3.3V 3.3V 3.3V 3.3V 0V
Mixed voltage supply 3.3V 3.3V or 2.5V 3.3V 3.3V or 2.5V 0 V
2.5V 2.5V 2.5V 2.5V 2.5V 0 V
a. V
CC
is the positive power supply of the device core and input circuitry. V
CC
voltage defines the input threshold and levels
b. V
CCA
is the positive power supply of the bank A outputs. V
CCA
voltage defines bank A output levels
c. V
CCB
is the positive power supply of the bank B outputs. V
CCB
voltage defines bank B output levels. V
CCB
is internally connected to V
CC
.
d. V
CCC
is the positive power supply of the bank C outputs. V
CCC
voltage defines bank C output levels
Table 3: Function Table (Controls)
Control Default 0 1
FSELA 0 f
QA0:2
= f
REF
f
QA0:2
= f
REF
÷ 2
FSELB 0 f
QB0:2
= f
REF
f
QB0:2
= f
REF
÷ 2
FSELC 0 f
QC0:3
= f
REF
f
QC0:3
= f
REF
÷ 2
MR/OE 0 Outputs enabled Internal reset
Outputs disabled (tristate)
Table 4: Absolute Maximum Ratings
a
Symbol Characteristics Min Max Unit Condition
V
CC
Supply Voltage -0.3 4.6 V
V
IN
DC Input Voltage -0.3 V
CC
+0.3 V
V
OUT
DC Output Voltage -0.3 V
CC
+0.3 V
I
IN
DC Input Current ±20 mA
I
OUT
DC Output Current ±50 mA
T
S
Storage temperature -40 125 °C
a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not
implied.
Table 5: General Specifications
Symbol Characteristics Min Typ Max Unit Condition
V
TT
Output Termination Voltage V
CC
÷ 2 V
MM ESD Protection (Machine Model) 200 V
HBM ESD Protection (Human Body Model) 2000 V
LU Latch–Up Immunity 200 mA
C
PD
Power Dissipation Capacitance 10 pF Per output
C
IN
Input Capacitance 4.0 pF
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

MPC9456FA

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
Clock Buffer 2.5 3.3V 250MHz Clock Generator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet