Commercial and Industrial Temperature Range
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
2
Description:
The IDT70V27 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit and wider word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (
CE0 and CE1) permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these
devices typically operate on only 500mW of power. The IDT70V27 is
packaged in a 100-pin Thin Quad Flatpack (TQFP) and a 144-pin Fine
Pitch BGA (fp BGA).
Pin Configurations
(1,2,3)
NOTES:
1. All V
DD pins must be connected to power supply.
2. All V
SS pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
INDEX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1009998 979695 949392 9190 8988 8786 8584 838281 8079 7877 76
IDT70V27PF
PN100-1
(4)
100-PIN TQFP
TOP VIEW
(5)
V
SS
OE
R
R/W
R
SEM
R
CE
1R
CE
0R
NC
NC
V
SS
A
12R
A
13R
A
11R
A
10R
A
9R
A
14R
NC
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
V
SS
UB
R
LB
R
3603 drw 02
I/O
15L
V
SS
OE
L
R/W
L
SEM
L
CE
1L
CE
0L
V
DD
NC
A
14L
A
13L
NC
NC
A
12L
A
11L
A
10L
A
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
UB
L
LB
L
V
SS
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
I
/
O
2
R
I
/
O
0
R
I
/
O
0
L
V
S
S
I
/
O
2
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
3
L
I
/
O
1
R
I
/
O
7
R
N
C
I
/
O
8
R
I
/
O
9
R
I
/
O
8
L
I
/
O
9
L
I
/
O
6
R
A
7
R
A
8
L
A
7
L
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
I
N
T
R
B
U
S
Y
R
M
/
S
B
U
S
Y
L
I
N
T
L
N
C
A
0
L
A
2
L
A
3
L
A
5
L
A
6
L
A
1
L
A
4
L
A
8
R
V
S
S
V
D
D
I
/
O
1
L
V
D
D
V
S
S
07/29/04
