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70V27S15PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Commercial and Industrial Temperature Range
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
7
AC Test Conditions
Figure 1. AC Output Test Load
3603 drw 04
590Ω
30pF
435Ω
3.3V
DATA
OUT
BUSY
INT
590Ω
5pF*
435Ω
3.3V
DATA
OUT
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
3603 tbl 11
Figure 2. Output Test Load
(for t
LZ, tHZ, tWZ, tOW)
*Including scope and jig
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,6)
(VDD = 3.3V ± 0.3V)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. V
DD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 90mA (Typ.)
3. At f = f
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
70V27X35
Com'l & Ind
70V27X55
Com'l Only
Symbol Parameter Test Condition Version
Typ.
(2)
Max.
Typ.
(2)
Max. Unit
I
DD
Dynamic Operating Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L
135
135
235
190
125
125
225
180
mA
IND'L S
L
____
135
____
235
____
____
____
____
I
SB1
Standby Current
(Both Ports - TTL Level
Inp uts)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L
22
22
45
35
15
15
40
30
mA
IND'L S
L
____
22
____
45
____
____
____
____
I
SB2
Standby Current
(One Port - TTL Level
Inp uts)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L
85
85
140
125
75
75
140
125
mA
IND'L
S
L
____
85
____
140
____
____
____
____
I
SB3
Full Standby Current (Both
Ports - All CMOS Level
Inp uts)
Both Ports CE
L
and
CE
R
> V
DD
- 0.2V
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
DD
- 0.2V
COM'L S
L
1.0
0.2
6
3
1.0
0.2
6
3
mA
IND'L
S
L
____
0.2
____
6
____
____
____
____
I
SB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
DD
- 0.2V
(5)
SEM
R
= SEM
L
> V
DD
- 0.2V
V
IN
> V
DD
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
COM'L S
L
85
85
135
120
75
75
135
120
mA
IND'L
S
L
____
85
____
135
____
____
____
____
3603 tbl 10b
Commercial and Industrial Temperature Range
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
8
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
5. Refer to Chip Enable Truth Table.
70V27X15
Com'l Only
70V27X20
Com'l & Ind
70V27X25
Com'l Only
UnitSymbol Parameter Min. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 15
____
20
____
25
____
ns
t
AA
Address Access Time
____
15
____
20
____
25 ns
t
ACE
Chip Enable Access Time
(3 )
____
15
____
20
____
25 ns
t
ABE
Byte Enable Access Time
(3 )
____
15
____
20
____
25 ns
t
AOE
Output Enable Access Time
____
10
____
12
____
15 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Outp ut Lo w-Z Time
(1,2)
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
12
____
12
____
15 ns
t
PU
Chip Enable to Power Up Time
(2,5)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2,5)
____
15
____
20
____
25 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
15
____
ns
t
SAA
Semaphore Address Access Time
____
15
____
20
____
35 ns
3603 tbl 12a
70V27X35
Com'l & Ind
70V27X55
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 35
____
55
____
ns
t
AA
Address Access Time
____
35
____
55 ns
t
ACE
Chip Enable Access Time
(3)
____
35
____
55 ns
t
ABE
Byte Enable Access Time
(3)
____
35
____
55 ns
t
AOE
Output Enable Access Time
____
20
____
30 ns
t
OH
Output Hold from Address Change 3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
20
____
25 ns
t
PU
Chip Enable to Power Up Time
(2,5)
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2,5)
____
45
____
50 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)15
____
15
____
ns
t
SAA
Semaphore Address Access Time
____
45
____
65 ns
3603 tbl 12b
Commercial and Industrial Temperature Range
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
9
Waveform of Read Cycles
(5)
Timing of Power-Up Power-Down
NOTES:
1. Timing depends on which signal is asserted last: CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first: CE, OE, LB, or UB.
3. t
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE, tACE, tAA or tBDD.
5. SEM = V
IH.
6. Refer to Chip Enable Truth Table.
t
RC
R/W
CE
ADDR
t
AA
OE
UB, LB
3603 drw 05
(4)
t
ACE
(4)
t
AOE
(4)
t
ABE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
(6)
CE
3603 drw 06
t
PU
I
CC
I
SB
t
PD
50% 50%
(6)
,
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

70V27S15PF

Mfr. #:
Buy 70V27S15PF
Manufacturer:
IDT
Description:
SRAM 32Kx16 3.3V DUAL- PORT RAM
Lifecycle:
New from this manufacturer.
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