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74LVC273PW/AUJ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
74LVC273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 31 December 2012 6 of 17
NXP Semiconductors
74LVC273
Octal D-type flip-flop with reset; positive-edge trigger
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation
delay
CP to Qn; see Figure 5
[2]
V
CC
= 1.2 V - 18 - - - ns
V
CC
= 1.65 V to 1.95 V 2.5 9.7 19.2 2.5 22.2 ns
V
CC
= 2.3 V to 2.7 V 1.8 4.9 9.9 1.8 11.4 ns
V
CC
= 2.7 V 1.5 4.5 8.4 1.5 10.5 ns
V
CC
= 3.0 V to 3.6 V 1.5 4.1 8.2 1.5 10.5 ns
t
PHL
HIGH to LOW
propagation
delay
MR to Qn; see Figure 6
V
CC
= 1.2 V - 18 - - - ns
V
CC
= 1.65 V to 1.95 V 2.4 10.2 20.4 2.4 23.5 ns
V
CC
= 2.3 V to 2.7 V 1.7 5.2 10.5 1.7 12.1 ns
V
CC
= 2.7 V 1.5 4.7 8.9 1.5 11.5 ns
V
CC
= 3.0 V to 3.6 V 1.5 4.3 8.7 1.5 11.0 ns
t
W
pulse width clock HIGH or LOW; see Figure 5
V
CC
= 1.65 V to 1.95 V 6.0 - - 6.0 - ns
V
CC
= 2.3 V to 2.7 V 5.0 - - 5.0 - ns
V
CC
= 2.7 V 5.0 1.8 - 5.0 - ns
V
CC
= 3.0 V to 3.6 V 4.0 1.2 - 4.0 - ns
master reset LOW; see Figure 6
V
CC
= 1.65 V to 1.95 V 6.0 - - 6.0 - ns
V
CC
= 2.3 V to 2.7 V 5.0 - - 5.0 - ns
V
CC
= 2.7 V 5.0 1.7 - 5.0 - ns
V
CC
= 3.0 V to 3.6 V 4.0 1.2 - 4.0 - ns
t
rec
recovery time MR to CP; see Figure 6
V
CC
= 1.65 V to 1.95 V 2.0 - - 2.0 - ns
V
CC
= 2.3 V to 2.7 V 2.0 - - 2.0 - ns
V
CC
= 2.7 V 2.0 1.0 - 2.0 - ns
V
CC
= 3.0 V to 3.6 V 2.0 1.0 - 2.0 - ns
t
su
set-up time Dn to CP; see Figure 7
V
CC
= 1.65 V to 1.95 V 5.0 - - 5.0 - ns
V
CC
= 2.3 V to 2.7 V 3.5 - - 3.5 - ns
V
CC
= 2.7 V 3.0 1.0 - 3.0 - ns
V
CC
= 3.0 V to 3.6 V 1.0 0.0 - 1.0 - ns
t
h
hold time Dn to CP; see Figure 7
V
CC
= 1.65 V to 1.95 V 3.0 - - 3.0 - ns
V
CC
= 2.3 V to 2.7 V 2.5 - - 2.5 - ns
V
CC
= 2.7 V 2.0 0.2 - 2.0 - ns
V
CC
= 3.0 V to 3.6 V 1.0 0.0 - 1.0 - ns
74LVC273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 31 December 2012 7 of 17
NXP Semiconductors
74LVC273
Octal D-type flip-flop with reset; positive-edge trigger
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volt
N = number of inputs switching
(C
L
V
CC
2
f
o
) = sum of the outputs
11. Waveforms
f
max
maximum
frequency
see Figure 5
V
CC
= 1.65 V to 1.95 V 80 - - 64 - MHz
V
CC
= 2.3 V to 2.7 V 100 - - 80 - MHz
V
CC
= 2.7 V 150 - - 150 - MHz
V
CC
= 3.0 V to 3.6 V 150 230 - 150 - MHz
t
sk(o)
output skew time V
CC
= 3.0 V to 3.6 V
[3]
- - 1.0 - 1.5 ns
C
PD
power dissipation
capacitance
per flip-flop; V
I
= GND to V
CC
[4]
V
CC
= 1.65 V to 1.95 V - 14.0 - - - pF
V
CC
= 2.3 V to 2.7 V - 17.7 - - - pF
V
CC
= 3.0 V to 3.6 V - 21.0 - - - pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 5. Clock (CP) to output (Qn) propagation delays, the clock pulse width, and the maximum frequency
mna765
CP input
Qn
output
t
PHL
t
PLH
t
W
V
M
V
OH
V
I
GND
V
OL
V
M
V
M
1/f
max
74LVC273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 31 December 2012 8 of 17
NXP Semiconductors
74LVC273
Octal D-type flip-flop with reset; positive-edge trigger
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 6. Master reset (MR) pulse width, the master reset to output (Qn) propagation delays, and the master reset
to clock (CP) recovery time
mna464
MR
input
CP
input
Qn
output
t
PHL
t
W
t
rec
V
M
V
I
GND
V
I
V
OL
GND
V
M
V
M
V
OH
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 7. Data set-up and hold times for the data input (Dn)
mna767
GND
GND
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
I
V
OH
V
OL
V
I
Qn output
CP input
Dn input
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

74LVC273PW/AUJ

Mfr. #:
Buy 74LVC273PW/AUJ
Manufacturer:
NXP Semiconductors
Description:
Flip Flops Octal Dtype flipflop positive-edgetrigge
Lifecycle:
New from this manufacturer.
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